System and method for efficient data mirroring in a pair of storage devices

• US 6,813,688 B2
• Filed: 12/04/2000
• Issued: 11/02/2004
• Est. Priority Date: 12/04/2000
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Wu, Chia Y., Lee, Whay S., Talagala, Nisha D.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US09/729,762
• Publication Number:
  US 20020103966A1
• Time in Patent Office: 1,429 Days
• Field of Search: 711/114
• US Class Current: 711/114
• CPC Class Codes: G06F 11/2087 with a common controller

Abstract

A system may include mirroring logic, a controller, and first and second devices (e.g., data storage devices). The first and second devices may include multiple registers. The mirroring logic may be configured in a first mode wherein the mirroring logic allows the registers of the first device to be accessed from the controller and prevents the registers of the second device from being accessed from the controller. The mirroring logic may be configured in a second mode wherein the mirroring logic allows the registers of the second device to be accessed from the controller and prevents the registers of the first device from being accessed. The first and second devices may be configured via the mirroring logic such that the first and second devices are selected simultaneously. When selected simultaneously, the first and second devices may carry out a subsequently issued command substantially simultaneously.

Claims

1. A circuit, comprising:

mirroring logic configured to couple to a host controller, a first device, and a second device, wherein each of the first and second devices comprises a plurality of registers; and

wherein the mirroring logic is configurable to operate in;

a first connect mode wherein the mirroring logic allows the registers of the first device to be accessed from the host controller and prevents the registers of the second device from being accessed from the host controller when the first and second devices are both active on the same communication channel; and

a second connect mode wherein the mirroring logic allows the registers of the second device to be accessed from the host controller and prevents the registers of the first device from being accessed from the host controller when the first and second devices are both active on the same communication channel; and

a third connect mode wherein the mirroring logic allows the registers of both the first device and second device to be accessed from the host controller;

wherein the mirroring logic is configured to switch between said first, second and third connect modes in response to mode commands from the host controller.

2. The circuit as recited in claim 1, wherein the first and second devices are data storage devices.

3. The circuit as recited in claim 1, wherein the registers of the first and second devices are accessed via a plurality of control signals produced by the controller, and wherein the mirroring logic is coupled to receive a portion of the control signals and configured to selectively provide the portion of the control signals to the first and second devices.

4. The circuit as recited in claim 3, wherein in the first connect mode the mirroring logic provides the portion of the control signals to only the first device such that the registers of only the first device are accessed, and wherein in the second connect mode the mirroring logic provides the portion of the control signals to only the second device such that the registers of only the second device are accessed.

5. The circuit as recited in claim 4, wherein each of the first and second devices includes an AT Attachment (ATA) interface conforming to an ATA standard.

6. The circuit as recited in claim 5, wherein the control signals include ATA control signals, and wherein each of the first and second devices is configurable to be selected in response to register accesses via the ATA control signals, and wherein the first and second devices carry out received commands only when selected.

7. The circuit as recited in claim 6, wherein the ATA control signals include a plurality of ATA address signals, and wherein in the first connect mode the mirroring logic provides the ATA address signals to only the first device, and wherein in the second connect mode the mirroring logic provides the ATA address signals to only the second device.

8. The circuit as recited in claim 7, wherein each of the first and second devices is configurable to be selected dependent upon the ATA address signals.

9. The circuit as recited in claim 8, wherein the ATA address signals comprise a chip select 0 (CS0) signal, a chip select 1 (CS1), a device address bit 0 (DA0) signal, a device address bit 1 (DA1) signal, and a device address bit 2 (DA2) signal, and wherein the CS0 and CS1 signals are active low, and wherein the DA0, DA1, and DA2 signals are active high.

10. The circuit as recited in claim 1, wherein the mirroring logic is coupled to receive a first plurality of status signals from the first device and a second plurality of status signals from the second device, and wherein the mirroring logic is configured to produce a third plurality of status signals dependent upon the first and second pluralities of status signals.

11. The circuit as recited in claim 10, wherein the third connect mode is a simultaneous write mode, and wherein in the simultaneous write mode the mirroring logic is configured to:

(i) provide all of the control signals to both the first and second devices, and (ii) produce the third plurality of status signals by logically ANDing corresponding status signals of the first and second pluralities of status signals.

12. The circuit as recited in claim 11, wherein the first, second, and third pluralities of status signals comprise ATA status signals including a direct memory access request (DMARQ) signal, an interrupt request (INTRQ) signal, and an input/output ready (IORDY) signal, and wherein the DMARQ, INTRQ, and IORDY signals are active high.

13. The circuit as recited in claim 10, wherein the third connect mode is a normal mode, and wherein in the normal mode the mirroring logic is configured to:

(i) provide all of the control signals to both the first and second devices, and (ii) produce the third plurality of status signals by wiring together corresponding status signals of the first and second pluralities of status signals.

14. The circuit as recited in claim 13, wherein the first, second, and third pluralities of status signals comprise ATA status including a direct memory access request (DMARQ) signal, an interrupt request (INTRQ) signal, and an input/output ready (IORDY) signal, and wherein the DMARQ, INTRQ, and IORDY signals are active high.

15. A system, comprising:

a host controller configured to produce a plurality of control signals;

a first device and a second device accessible on the same communication channel, wherein each of the first and second devices comprise a plurality of registers accessed via the control signals; and

mirroring logic coupled to the first and second devices and to receive a portion of the control signals, wherein the mirroring logic is configurable to provide the portion of the control signals to;

(i) only the first device in a first mode so that the registers of the second device are not accessed, (ii) only the second device in a second mode so that the registers of the first device are not accessed, and (iii) both the first and second devices in a third mode so that the registers of both the first and second devices are accessed, wherein the mirroring logic is configured to switch between said first, second and third modes in response to mode commands from the host controller.

16. The system as recited in claim 15, wherein the first and second devices are data storage devices.

17. The system as recited in claim 15, wherein the mirroring logic is configured to allow both the first and second devices to be selected simultaneously.

18. The system as recited in claim 15, wherein the first and second devices have AT Attachment (ATA) interfaces conforming to an AT standard, and wherein the control signals are ATA control signals.

19. The system as recited in claim 18, wherein the AT control signals include a plurality of ATA address signals, and wherein the mirroring logic is configurable to provide the ATA address signals to:

(i) only the first device in the first mode so that the registers of the second device are not accessed, (ii) only the second device in the second mode so that the registers of the first device are not accessed, and (iii) both the first and second devices in the third mode so that the registers of both the first and second devices are accessed.

20. The system as recited in claim 19, wherein the first and second devices are configurable to be selected dependent upon the ATA address signals, and wherein the first and second devices carry out received commands only when selected.

21. The system as recited in claim 15, wherein the mirroring logic is coupled to receive a first plurality of status signals from the first device and a second plurality of status signals from the second device, and wherein the mirroring logic is configured to produce a third plurality of status signals dependent upon the first and second pluralities of status signals.

22. The system as recited in claim 21, wherein the third mode is a normal mode and in the normal mode the mirroring logic is configure to produce the third plurality of status signals by wiring together corresponding status signals of the first and second pluralities of status signals.

23. The system as recited in claim 21, wherein the third mode is a simultaneous write mode and in the simultaneous write mode the mirroring logic is configured to produce the third plurality of status signals by logically ANDing corresponding status signals of the first and second pluralities of status signals.

24. A system, comprising:

a pair of devices each having an AT Attachment (ATA) interface conforming to an ATA standard, wherein one of the pair of devices is configured as an ATA master device and the other device is configured as an ATA slave device on the same ATA channel; and

mirroring logic coupled to the pair of devices and to receive a plurality of ATA control signals, wherein the ATA control signals include a plurality of ATA address signals, and wherein the mirroring logic is configurable to operate in one of a plurality of modes comprising;

a first connect mode wherein the mirroring logic provides the ATA address signals to only the ATA master device;

a second connect mode wherein the mirroring logic provides the ATA address signals to only the ATA slave device; and

a third connect mode wherein the mirroring logic provides the ATA address signals to both the ATA master device an the ATA slave device to concurrently address both the ATA master device and the ATA slave device.

25. The system as recited in claim 24, wherein each of the pair of devices is a hard disk drive.

26. The system as recited in claim 24, wherein the mirroring logic is configured to allow both the first and second devices to be selected simultaneously.

27. The system as recited in claim 24, wherein each of the pair of devices is configurable to be selected dependent upon the ATA address signals, and wherein a selected one of the pair of device carries out received commands.

28. The system as recited in claim 24, wherein the AT address signals comprise a chip select 0 (CS0) signal, a chip select 1 (CS1), a device address bit 0 (DA0) signal, a device address bit 1 (DA1) signal, and a device address bit 2 (DA2) signal, and wherein the CS0 and CS1 signals are active low, and wherein the DA0, DA1, and DA2 signals are active high.

29. The system as recited in claim 24, wherein the mirroring logic is configured to enter the first connect mode in response to receiving three consecutive writes to the ATA features register.

30. The system as recited in claim 24, wherein the mirroring logic is configured to enter the second connect mode in response to receiving three consecutive writes to the ATA device/control register.

31. The system as recited in claim 24, wherein the mirroring logic is coupled to receive a first plurality of ATA status signals from the master device and a second plurality of ATA status signals from the slave device, and wherein the mirroring logic is configured to produce a third plurality of ATA status signals dependent upon the first and second pluralities of ATA status signals.

32. The system as recited in claim 31, wherein the third connect mode is a normal mode, and wherein in the normal mode the mirroring logic:

(i) provides the ATA address signals to both the master and slave devices, and (ii) produces the third plurality of ATA status signals by wiring together corresponding ATA status signals of the first and second pluralities of ATA status signals.

33. The system as recited in claim 32, wherein the first, second, and third pluralities of ATA status signals comprise a direct memory access request (DMARQ) signal, an interrupt request (INTRQ) signal, and an input/output ready (IORDY) signal, and wherein the DMARQ, INTRQ, and IORDY signals are active high.

34. The system as recited in claim 32, wherein the mirroring logic is configured to enter the normal mode in response to receiving three consecutive writes to the ATA cylinder low register.

35. The system as recited in claim 31, wherein the third connect mode is a simultaneous write mode, and wherein in the simultaneous write mode the mirroring logic:

(i) provides the ATA address signals to both the master and slave devices, and (ii) produces the third plurality of ATA status signals by logically ANDing corresponding ATA status signals of the first and second pluralities of ATA status signals.

36. The system as recited in claim 35, wherein the first, second, and third pluralities of ATA status signals comprise a direct memory access request (DMARQ) signal, an interrupt request (INTRQ) signal, and an input/output ready (IORDY) signal, and wherein the DMARQ, INTRQ, and IORDY signals are active high.

37. The system as recited in claim 35, wherein the mirroring logic is configured to enter the simultaneous write mode in response to receiving three consecutive writes to the ATA cylinder high register.

38. In a system comprising a controller a first storage device and a second storage device, wherein each of the pair of devices comprises a plurality of registers mapped to the same register address space, a method for configuring the first storage device and the second storage device to carry out a command from the controller simultaneously, the method comprising:

performing at least the following actions to carry out the command from the controller simultaneously on the first and second storage devices;

writing to a first register in the address space to select the first storage device to respond to commands;

while the first storage device is selected to respond to commands, preventing the registers of the first storage device from being accessed;

while the registers of the first storage device are prevented from being accessed, writing to the first register in the address space to select the second storage device to respond to commands so that both the first storage device and the second storage device are selected to respond to commands;

while both the first and second storage devices are selected to respond to commands, allowing the registers of both the first storage device and the second storage device to be accessed; and

while the registers of both the first and second storage devices are allowed to be accessed, writing a command to a command register in the register address space, wherein the first storage device and the second storage device receive the command and both carry out the command approximately simultaneously.

39. The method as recited in claim 38, wherein said writing to a first register in the address space to select the first storage device comprise writing a first value to corresponding registers of both the first storage device and the second storage device, wherein the first value selects the first storage device.

40. The method as recited in claim 38, wherein the registers of the first storage and the second storage devices are accessed via a plurality of control signals produced by the controller, and wherein said preventing the registers of the first storage device from being accessed comprises providing a portion of the control signals to only the second storage device such that the registers of the first storage device are not accessed.

41. The method as recited in claim 38, wherein said writing to the first register in the address space to select the second storage device comprises writing a second value to a register of the second storage device, wherein the second value selects the second storage device.

42. The method as recited in claim 38, wherein the registers of the first storage and second storage devices are accessed via a plurality of control signals produced by the controller, and wherein said allowing the registers of both the first storage device and the second storage device to be accessed comprise providing the control signals to both the first storage device and the second storage device such that the registers of the both the first storage device and the second storage device are accessed.

43. The method as recited in claim 38, wherein the command is a write command.

44. The method as recited in claim 43, further comprising:

determining if the first storage device is ready to receive data;

determining if the second storage device is ready to receive data;

performing the following if both the first storage device and the second storage device are ready to receive data;

allowing the registers of both the first storage device and the second storage device to be accessed; and

writing a block of data to corresponding data registers of the first storage device and the second storage device, wherein the first storage device and the second storage device store the data approximately simultaneously.

45. The method of claim 44, wherein said determining if the first storage device is ready to receive data comprises:

preventing the registers of the second storage device from being accessed; and

while the registers of the second storage device are prevented from being accessed, reading a value from a status register of the first storage device.

46. The method of claim 44, wherein said determining if the second storage device is ready to receive data comprises:

preventing the registers of the first storage device from being accessed; and

while the registers of the first storage device are prevented from being accessed, reading a value from a status register of the second storage device.

47. The method of claim 38, wherein said controller is an AT Attachment (ATA) controller and said first and second storage devices are ATA storage devices both coupled to the same port of said ATA controller.

48. A method for communicating with devices, comprising:

performing at least the following actions to carry out a same command on multiple devices;

sending a first communication to a first device configured as a master device, wherein said communication indicates that the first device, but not a second device configured as a slave device on the same communication channel as the master device, is selected to respond to subsequent communications;

subsequent to said sending a first communication, sending a second communication to the second device, wherein the second communication indicates that the second device, but not the first device, is selected to respond to subsequent communications, wherein said sending a second communication is performed while preventing the first device from recognizing the second communication so that both the first device and the second device are selected to respond to subsequent communications; and

subsequent to said sending a second communication and while both the first device and the second device are selected to respond to subsequent communications, sending a third communication to both the first device and the second device, wherein both the first device and the second device respond to the third communication.

49. The method as recited in claim 48, wherein said sending a first communication comprises writing a value to corresponding registers of both the first device and the second device, wherein the value selects the first device.

50. The method as recited in claim 48, said preventing the first device from receiving the second communication comprises providing a portion of communication control signals to only the second device such that the first device does not recognize the second communication.

51. The method as recited in claim 48, wherein said sending a second communication comprises writing a value to a register of the second device, wherein the second value selects the second device.

52. The method as recited in claim 48, further comprising:

determining if the first device is ready to receive data;

determining if the second device is ready to receive data; and

if both the first device and the second device are ready to receive data, communicating a block of data to the first device and the second device while both the first device and the second device are selected, wherein the first storage device and the second storage device both store the data.

53. The method of claim 52, wherein said determining if the first device is ready to receive data comprises:

while preventing the second device from recognizing communications, reading a value from a status register of the first device.

54. The method of claim 52, wherein said determining if the second device is ready to receive data comprises:

while preventing the first device from recognizing communications, reading a value from a status register of the second device.

55. The method of claim 48, wherein said first and second devices are ATA storage devices both coupled to the same port of an ATA controller.