Scan interface chip (SIC) system and method for scan testing electronic systems

• US 6,813,739 B1
• Filed: 04/04/2000
• Issued: 11/02/2004
• Est. Priority Date: 04/04/2000
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Grannis, III, Louis C.
• Primary Examiner(s): Moise, Emmanuel L.
• Assistant Examiner(s): Dooley, Matthew C.
• Application Number:
  US09/543,023
• Time in Patent Office: 1,673 Days
• Field of Search: 714/726, 714/727, 714/729, 714/733, 714/734
• US Class Current: 714/729
• CPC Class Codes: G01R 31/2815 Functional tests, e.g. boundary scans, using the normal I/O contacts contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning

Abstract

A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Claims

1. A scan test interface comprising:

a scan test interface register for storing information related to scan test operations;

a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;

a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;

a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain; and

a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain and a general purpose Input/Ouput port for transmitting general purpose signals to downstream devices, wherein said selection circuit further comprises an Input/Ouput selection circuit for selecting said general purpose Input/Output port as an input or output.

2. The scan test interface of claim 1 wherein said general purpose Input/Output port is independently programmed to operate as an input, an output or bi-directional I/O.

3. The scan test interface of claim 1 wherein said general purpose Input/Output port is individually programmed via a mode register bit to be either an Input or an Output.

4. The scan test interface of claim 3 wherein said general purpose Input/Output port is used as a bi-directional port through programming sequences in which a mode register bit is switched off and on to control said general purpose Input/Output port to function as an input or an output at different sequencing times.

5. The scan test interface of claim 1 wherein said general purpose Input/Output port is defined as a pseudo open-collector output.

6. The scan test interface of claim 1 wherein said general purpose Input/Output port includes a 3.3, low voltage transistor-transistor logic (TTL) circuit with a logic switching level is of 2.0 Vih volts that operates properly in lower voltage applications.

7. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices;

facilitating flexible scan test operations including support for providing general purpose Input/Output signals;

communicating general purpose Input/Output signals via a general Input/Output port;

programming said general purpose Input/Output port to operate as an input or an output port;

accommodating bi-directional general purpose signals by alternating operation of said general purpose Input/Output port as an input port or an output port; and

tracking the designation of said general purpose Input/Output port as an input or output.

8. A scan test interface method of claim 7 further comprising using an Input/Output selection circuit to perform selection of a general purpose Input/Output port to function as an input or an output port.

9. A scan test interface method of claim 7 further comprising switching on and off a mode register bit is switched on and off at appropriate times through programming sequences.

10. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices;

facilitating flexible scan test operations including support for providing general purpose Input/Output signals; and

utilizing an Input/Output register to track a general purpose Input/Output port as an input or output.

11. The scan test interface method of claim 10 implemented with a multi-drop scan interface chip (SIC) scan test system comprising:

a first plurality of downstream scannable devices arranged in a first scan test chain, said first plurality of downstream scannable devices located on a first printed circuit board;

a first SIC coupled to said first plurality of downstream scannable devices, said SIC communicates a test signal to said first scan test chain, the first SIC located on the first printed circuit board;

a second plurality of downstream scannable devices arranged in a second scan test chain, said second plurality of downstream scannable devices located on a second printed circuit board;

a second SIC coupled to said second plurality of downstream scannable devices, said SIC communicates a test signal to said second scan test chain, the second SIC located on the second printed circuit board; and

a scan test system controller coupled to said first SIC and said second SIC, said scan test system controller communicating said scan test signal to and from said first SIC and said second SIC.

12. A multi-drop SIC scan test system of claim 11 wherein at least one of said first SIC and said second SIC communicates to said scan test chain a logical copy of said scan test signal received by said SIC from said scan test system controller.

13. A multi-drop SIC scan test system of claim 11 wherein at least one of said first SIC and said second SIC transmits and receives general purpose input and outputs signals.

14. A multi-drop SIC scan test system of claim 11 wherein at least one of said first SIC and said second SIC facilitates programmatic control of signals utilized to assist non-compliant devices to function compliantly during scan test operations.

15. A multi-drop SIC scan test system of claim 11 wherein at least one of said first SIC and said second SIC supports retrieval of information regarding a printed circuit board (PCB).

16. A multi-drop SIC scan test system of claim 11 wherein at least one of said first SIC and said second SIC supports the return of debug information to said scan test system controller.

17. A multi-drop SIC scan test system of claim 11 wherein at least one of said first SIC and said second SIC includes both full scan and an input NAND tree features for performing internal SIC testing functions.

18. A scan test interface method of claim 10 further comprising the step of transmitting general purpose Input/Output signals.

19. The A scan test interface method of claim 10 wherein

facilitating flexible scan test operations includes automatically retrieving information regarding a device included on a printed circuit board.

20. The scan test interface method of claim 10 further comprising the step of determining automatically the configuration of devices being scan tested.

21. A scan test interface comprising:

a scan test interface register for storing information related to scan test operations;

a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;

a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;

a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain;

a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain; and

a program scan interface including a communication port for a program scan interface signal to facilitates programmatic control of special scan test support signals.

22. The scan test interface of claim 21 wherein said board interface provides signals that enable scannable devices for operation in a scan test mode.

23. The scan test interface of claim 21 wherein said board interface provides a signal that controls whether a functional reset signal is utilized to reset scan test features of a downstream device during scan test operations.

24. A scan test interface comprising:

a scan test interface register for storing information related to scan test operations;

a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;

a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;

a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain; and

a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain and facilitates programmatic control of special scan test support signals, wherein said board interface includes a Test Chain Enable Not Output (TCENO) port that provides a communication port for special scan test support signals.

25. The scan test interface of claim 24 wherein said special scan test support signals include TCENO signals that are active low outputs from a SIC and are included as compliance facilitating signals for scannable devices.

26. The scan test interface of claim 25 wherein said TCENO signals are inverted copies of the corresponding bit in the chain enable register.

27. The scan test interface of claim 24 wherein said special scan test support signals include TCENO signals that are active low outputs from a SIC and are included as scan test enable facilitating signals for scan devices that require external stimulus to enable their scan functions.

28. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices;

facilitating flexible scan test operations including facilitating programmatic control of signals utilized to assist non-compliant devices to function compliantly during scan test operations; and

providing a scan test compliance signal that facilitates a non compliant scannable device to function compliantly during scan test operations, wherein said scan test compliance signal include a signal that copies the logical values of another signal.

29. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices;

facilitating flexible scan test operations including facilitating programmatic control of signals utilized to assist non-compliant devices to function compliantly during scan test operations; and

providing a scan test compliance signal that facilitates a non compliant scannable device to function compliantly during scan test operations, wherein said scan test compliance signal[s] include a signal that copies the inverse logical values of another signal.

30. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices; and

facilitating flexible scan test operations including facilitating programmatic control of signals utilized to assist non-compliant devices to function compliantly during scan test operations; and

providing a scan test compliance signal that facilitates a non compliant scannable device to function compliantly during scan test operations, wherein said scan test compliance signals is a TCENO signal of a SIC chip output on a TCENO port.

31. A scan test interface comprising:

a scan test interface register for storing information related to scan test operations;

a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;

a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;

a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain;

a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain; and

a number in can (NIC) circuit coupled to said board interface, said NIC circuit supports retrieval of information regarding a PCB.

32. The scan test interface of claim 31 wherein said NIC circuit facilitates retrieval of information associated with downstream scan test devices including a unique number in an electronically readable device on a board said scan test interface services.

33. The scan test interface of claim 31 wherein said retrieved information enables scan test software to configure itself rather than needing manual input of this information or empirically extracting the information.

34. The scan test interface of claim 31 wherein said board interface comprises a NIC Interface including a NIC input/output (I/O) port that provide a communication interface for NIC signals.

35. The scan test interface of claim 34 wherein said NIC signal is used to read the contents of a NIC device coupled to a scan test chain, said contents allows scan test software to identify information associated with scannable hardware including the contents of a NIC device, the board type, revision level, the part number, design level and serial number.

36. The scan test interface of claim 31 wherein said scan test interface register includes a NIC control register for storing NIC information.

37. The scan test interface of claim 31 wherein said NIC circuit comprises a NIC sequence circuit for providing sequencing control over retrieval of NIC information associated with components included on a printed circuit board said scan test interface services.

38. The scan test interface of claim 31 wherein said NIC circuit comprises a NIC selection circuit that selects a NIC port included in said board interface.

39. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices; and

facilitating flexible scan test operations including automatically retrieving information regarding a device included on a printed circuit board;

reading the contents of a device including number in can (NIC) information comprising the board type, revision level, and serial number;

identifying hardware components without booting up the operating system;

utilizing extracted NIC information to automatically configure test software without manual input of the information or empirically extracting the information;

providing precautions to protect scan test interface a (NIC) input output (I/O) port from damage; and

storing retrieved NIC information.

40. A scan test interface method comprising:

receiving scan test information from upstream scan test devices;

transmitting scan test information to downstream devices;

receiving scan test information from downstream devices;

transmitting scan test information to upstream scan test devices; and

facilitating flexible scan test operations including automatically retrieving information regarding a device included on a printed circuit board;

storing number in can (NIC) information in a memory device; and

interfacing with said memory device.