Method of determining charge loss activation energy of a memory array

• US 6,813,752 B1
• Filed: 11/26/2002
• Issued: 11/02/2004
• Est. Priority Date: 11/26/2002
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tanpairoj, Kulachet, Zheng, Wei, Randolph, Mark W., Hamilton, Darlene G., Hsia, Edward
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US10/306,667
• Time in Patent Office: 707 Days
• Field of Search: 716/4, 714/720, 714/718, 700/82, 438/758, 438/593, 438/3, 438/17, 430/30, 400/124.05, 365/201, 365/185.24, 365/185.18, 365/185.03, 365/185.01, 361/311, 356/632, 324/658, 298/52, 257/393, 257/295, 252/519.2, 174/264
• US Class Current: 716/136
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.

Claims

1. A method of determining charge loss activation energy for a technology, comprising:

a) programming a first memory array and a second memory array with a pattern for testing charge loss, wherein said first and second memory arrays represent a given technology;

b) calculating respective bake times for said first and said second memory arrays to experience an arbitrary amount of charge loss at respective first and second temperatures; and

c) calculating charge loss activation energy for the technology represented by the first and second memory arrays, based on said respective bake times to lose said given amount of charge at said respective first and second temperatures.

2. A method according to claim 1, wherein said b) comprises:

b1) baking said first memory array at said first temperature for a plurality of time intervals;

b2) calculating a loss of charge for each of said time intervals; and

b3) calculating said bake time for said first memory array to experience said arbitrary amount of charge loss, based on said calculation in said b2).

3. A method according to claim 1, wherein:

said a) further comprises cycling said first memory array and said second memory array by repeatedly erasing and reprogramming said first memory array and said second memory array.

4. A method according to claim 1, wherein:

said a) further comprises cycling different portions of said first memory array and said second memory array for different numbers of cycles, wherein said charge loss activation energy is calculated for each of said different numbers of cycles.

5. A method according to claim 1, wherein said a) further comprises:

programming cells of said first memory array and said second memory array to a pre-determined delta threshold voltage.

6. A method according to claim 1, wherein said a) further comprises programming a plurality of regions of said first memory array to a plurality of distinct threshold voltages.

7. A method according to claim 1, wherein said first and said second memory arrays are operable to store a plurality of bits per memory cell.

8. A method according to claim 1, wherein said pattern comprises two distinct values per memory cell.

9. A method according to claim 1, wherein said c) comprises:

calculating said charge loss activation energy using data from substantially all of said first memory array and said second memory array.

10. A method according to claim 1, wherein said c) comprises:

calculating said charge loss activation energy using data from a portion of said first memory array and said second memory array.

11. A method according to claim 10, wherein said portion comprises a group of word lines that are separated from each other by a pre-determined number of wordlines.

12. The method of claim 1, further comprising applying said charge loss activation energy for the technology represented by the first and second memory arrays to determine a figure of merit for the technology.

13. The method of claim 12, wherein the figure of merit comprises a projected number of times memory arrays of the technology may be reprogrammed.

14. The method of claim 12, wherein the figure of merit comprises suggested ranges of operating temperatures for the technology.

15. The method of claim 12, wherein the figure of merit comprises a projected amount of time a memory array will retain its charge for the technology.

16. A method of determining charge loss activation energy for a type of memory, comprising:

a) programming a first memory array on a first wafer with a pattern for testing charge loss, wherein memory cells of said memory array are programmed with two bits per cell;

b) baking said first memory array at a first temperature for a plurality of bake times;

c) calculating a charge loss for each of said bake times;

d) estimating a bake time for said first memory array to have an arbitrary amount of charge loss, based on said calculation in said c);

e) repeating said a)-d) for a second memory array on a second wafer at a second temperature, wherein said first and second memory arrays represent a type of memory; and

f) calculating said charge loss activation energy for the type of memory, based on said estimated bake times to lose said arbitrary amount of charge at said first temperature and said second temperature.

17. A method according to claim 16, further comprising:

repeating said a)-d) for additional memory arrays on additional wafers at additional temperatures and using data collected therefrom in said charge loss activation energy calculation in said f).

18. A method according to claim 16, wherein said a) comprises:

a1) programming a first plurality of cells of said first memory array to have a first distribution of voltage thresholds;

a2) programming a second plurality of cells of said first memory array to have a second distribution of voltage thresholds, wherein a difference between said first distribution and said second distribution is a pre-determined value.

19. A method according to claim 16, wherein said a) comprises programming said first memory array to a checkerboard pattern.

20. A method according to claim 16, wherein a value of said two bits is different from each other.

21. A method according to claim 16, wherein said f) comprises calculating said charge loss activation from a slope of a line formed by said estimated bake times in said d).

22. The method of claim 16, further comprising applying said charge loss activation energy for the type of memory represented by the first and second memory arrays to determine a figure of merit for the type of memory.

23. A method of determining charge loss activation energy for a flash memory, comprising:

a) programming a plurality of memory arrays on a respective plurality of wafers with a checkerboard pattern for testing charge loss wherein the plurality of memory arrays are representative of the flash memory;

b) calculating respective bake times for said plurality of memory arrays to experience an arbitrary amount of charge loss at respective temperatures, wherein each wafer is baked at a unique temperature; and

c) calculating charge loss activation energy for the flash memory that is represented by the plurality of memory arrays, based on said respective bake times.

24. A method according to claim 23, wherein said b) comprises:

b1) baking a first memory array of said plurality at a first temperature for a plurality of bake times;

b2) measuring threshold voltages for memory cells of said first memory array programmed to a first value for each of said plurality of bake times;

b3) measuring threshold voltages for memory cells of said first memory array programmed to a second value for each of said plurality of bake times;

b4) calculating actual charge loss, based on threshold voltage distributions created from said measurements in said b2) and b3); and

b5) estimating a bake time of said respective bake times for said first memory array to have said arbitrary amount of charge loss, based on said actual charge loss.

25. A method according to claim 23, wherein said plurality of wafers are manufactured from the same lot.

26. The method of claim 23, further comprising applying said charge loss activation energy for the flash memory represented by the plurality of memory arrays to determine a figure of merit for the flash memory.