Magnetic layer processing

• US 6,815,220 B2
• Filed: 01/30/2001
• Issued: 11/09/2004
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gardner, Donald S., Crawford, Ankur Mohan
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MANDALA, MICHELLE
• Application Number:
  US09/772,783
• Publication Number:
  US 20010031549A1
• Time in Patent Office: 1,379 Days
• Field of Search: 438/3, 438/57, 438/745, 427/128
• US Class Current: 438/3
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/32 Composite [nonstructural laminate] of inorganic material having metal-compound-containing layer and having defined magnetic layer

Abstract

A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.

Claims

1. A method comprising:

forming a first dielectric layer over a semiconductor substrate;

depositing a first magnetic layer comprising an amorphous alloy which includes cobalt over the first dielectric layer;

patterning the first magnetic layer using a mask;

forming a second dielectric layer over the first magnetic layer;

depositing a conductive layer over the second dielectric layer;

forming a third dielectric layer over the conductive layer; and

patterning a second magnetic layer over the third dielectric layer to put the second magnetic layer in contact with the first magnetic layer and to form an inductor as part of a semiconductor based integrated circuit.

2. The method of claim 1, wherein the amorphous alloy comprises cobalt and zirconium.

3. The method of claim 2, wherein the amorphous alloy comprises approximately 3 atomic percent to approximately 10 atomic percent zirconium.

4. The method of claim 1, wherein the amorphous alloy comprises cobalt, zirconium, and tantalum.

5. The method of claim 4, wherein the amorphous alloy comprises approximately 3 atomic percent to approximately 10 atomic percent zirconium and up to and including approximately 10 atomic percent tantalum.

6. The method of claim 5, wherein the amorphous alloy comprises approximately 4 atomic percent zirconium and approximately 4.5 atomic percent tantalum.

7. The method of claim 1, wherein the amorphous alloy comprises cobalt, zirconium, and niobium.

8. The method of claim 1, wherein the amorphous alloy comprises cobalt, zirconium, and a rare earth element.

9. The method of claim 8, wherein the amorphous alloy comprises cobalt;

zirconium; and

one of the group consisting of rhenium, neodymium, praseodymium and dysprosium.

10. The method of claim 8, wherein the amorphous alloy comprises approximately 3 atomic percent to approximately 10 atomic percent zirconium and up to and including approximately 3 atomic percent rhenium.

11. The method of claim 1, further comprising forming an underlying adhesion layer under the magnetic layer.

12. The method of claim 11, wherein the underlying adhesion layer comprises titanium.

13. The method of claim 1, further comprising depositing the magnetic layer in a fixed or switching magnetic field.

14. The method of claim 1, further comprising forming an overlying adhesion layer over the magnetic layer.

15. The method of claim 14, wherein the overlying adhesion layer comprises titanium or cobalt oxide.

16. The method of claim 14, wherein the overlying adhesion layer comprises oxidizing the magnetic layer.

17. The method of claim 1, wherein the patterning comprises etching an adhesion layer for the magnetic layer using a hydrofluoric acid solution.

18. The method of claim 1, wherein the patterning comprises wet etching the magnetic layer using a nitric acid solution.

19. The method of claim 1, further comprising annealing the magnetic layer in a magnetic field.

20. A method comprising:

forming a dielectric layer over a semiconductor substrate;

depositing a first adhesion layer over the dielectric layer;

depositing a magnetic material layer comprising an amorphous alloy which includes cobalt over the first adhesion layer;

depositing a second adhesion layer over the magnetic material layer; and

patterning the magnetic layer and both adhesion layers using a mask to form an inductor as part of a semiconductor based integrated circuit.

21. The method of claim 20, wherein the amorphous alloy comprises cobalt and zirconium.

22. The method of claim 20, wherein the depositing the magnetic material layer includes depositing magnetic material in a fixed or switching magnetic field.

23. The method of claim 20, wherein the patterning comprises wet etching the magnetic material layer using a nitric acid solution.

24. The method of claim 20, wherein the patterning comprises etching the adhesion layers using a hydrofluoric acid solution.