Method of manufacturing a semiconductor device having a memory cell section and an adjacent circuit section

• US 6,815,281 B1
• Filed: 09/22/2000
• Issued: 11/09/2004
• Est. Priority Date: 10/27/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Inoue, Ken, Hamada, Masayuki
• Primary Examiner(s): Nadav, Ori
• Assistant Examiner(s): Owens, Douglas W
• Application Number:
  US09/667,706
• Time in Patent Office: 1,509 Days
• Field of Search: 438/199, 438/200, 438/218, 438/221, 438/225, 438/220, 438/230, 438/231, 438/232, 438/233, 438/239
• US Class Current: 438/200
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions (10) and the gate surfaces (6) of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Claims

1. A method of manufacturing a DRAM-incorporated semiconductor device in which a DRAM section and a logic section are formed on a semiconductor substrate that is isolated into elements, said method comprising:

forming a metal film comprising one of cobalt and nickel directly on surfaces of highly doped source-drain regions and gate regions in said DRAM section and said logic section; and

heat treating said device to react said metal film with said surfaces to concurrently form a metal silicide layer in each of said DRAM section and said logic section.

2. The method of manufacturing a semiconductor device according to claim 1, wherein said metal film is formed over an entire surface of said substrate, and wherein said heat treating comprises:

heating said device at 500-600°

C.;

removing unreacted metal film with a mixed solution of sulfuric acid and hydrogen peroxide; and

heating said device at 800°

C.

3. The method of manufacturing a semiconductor device according to claim 2, wherein said metal film comprises cobalt.

4. The method of manufacturing a semiconductor device according to claim 1, wherein dopant implantation into gates are carried out concurrently with formation of the source-drain regions that constitute transistors in the DRAM section and the logic section, and thereby P-N gates are formed.

5. The method of manufacturing a semiconductor device according to claim 1, further comprising:

forming a bit contact connecting said DRAM section with a bit line and a contact plug connecting to said source-drain in said logic section, said bit contact and said contact plug comprising a metal material.

6. A method of manufacturing a DRAM-incorporated semiconductor device in which a DRAM section including a memory cell, decoder and sense amplifier, and a logic section are formed on a semiconductor substrate that is isolated into elements, said method comprising:

forming a transistor having a source including two regions different in impurity density from each other, and a drain including two regions different in impurity density from each other in said DRAM section;

forming a p-MOS transistor having a p-type gate, a source including two regions different in impurity density from each other, and a drain including two regions different in impurity density from each other in said logic section;

forming an n-MOS transistor having an n-type gate, a source including two regions different in impurity density from each other and a drain including two regions different in impurity density from each other in said logic section;

forming a metal film comprising either cobalt or nickel directly on substantially all surfaces of highly impurity-doped regions in said DRAM section and said logic section; and

heating said device to react said metal film with said surfaces to concurrently form a metal silicide layer in each of said DRAM section and said logic section.