Process for improving the etch stability of ultra-thin photoresist

• US 6,815,359 B2
• Filed: 03/28/2001
• Issued: 11/09/2004
• Est. Priority Date: 03/28/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Okoroanyanwu, Uzodinma, Gabriel, Calvin T.
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): Tran, Binh X.
• Application Number:
  US09/819,552
• Publication Number:
  US 20020142607A1
• Time in Patent Office: 1,322 Days
• Field of Search: 438/705, 438/706, 438/708, 438/709, 438/710, 438/725
• US Class Current: 438/705
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32139 using masks

Abstract

An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in accordance with the transformed feature, wherein an etch stability of the feature is increased by the hardened surface. The photoresist layer is provided at a thickness less than 0.25 μm, for use in deep ultraviolet lithography, or for use in extreme ultraviolet lithography.

Claims

1. A method of increasing an etch stability of a photoresist layer, the method comprising the steps of:

providing the photoresist layer at a thickness less than 0.25 μ

m, for use in vacuum ultraviolet lithography, deep ultraviolet lithography, or extreme ultraviolet lithography;

exposing the photoresist layer to a plasma, the photoresist layer including exposed surfaces; and

transforming the exposed surfaces to form a shell before using the photoresist layer to etch an underlying layer, wherein the shell increases the etch stability of the photoresist layer.

2. The method of claim 1, wherein the plasma has a plasma characteristic of approximately 50 mTorr chamber pressure.

3. The method of claim 2, wherein the plasma has plasma characteristics of approximately 100 sccm flow rate, 400 W radio frequency (RF) power, and 50°

C. lower electrode temperature.

4. The method of claim 1, wherein the etch stability is increased by 20-50% as compared to the etch stability of the photoresist layer before exposure to the plasma.

5. The method of claim 1, wherein the transforming step includes transforming the exposed surfaces by a depth of up to approximately 50 nm.

6. The method of claim 1, wherein the transforming step includes at least one of decarboxylation, cross-linking, and densification of the exposed surfaces to form the shell, the shell being hardened.

7. An integrated circuit fabrication process, the process comprising:

patterning a feature on a photoresist layer disposed over a substrate, the feature patterned in accordance with a pattern provided on a mask or reticle and a radiation at a deep ultraviolet or extreme ultraviolet lithographic wavelength;

developing the photoresist layer, the patterned photoresist layer including at least one feature having a top surface and side surfaces;

exposing the photoresist layer to a fluorine-based plasma densifier;

transforming the top surface and the side surfaces with the densifier to form a hardened surface; and

etching the substrate in accordance with the transformed feature, wherein the exposing step occurs after the developing step and before the etching step, and an etch stability of the feature is a function of the hardened surface.

8. The process of claim 7, further comprising providing the photoresist layer at a thickness of less than approximately 0.25 μ

m.

9. The process of claim 7, wherein the transforming step includes decarboxylation.

10. The process of claim 9, wherein the exposing step includes providing the fluorine-based plasma at operating parameters of 10-2000 sccm flow rate, 5-1000 mTorr chamber pressure, 50-2000 WRF power, and 20-80°

C. lower electrode temperature.

11. The process of claim 7, wherein the densifier is a flood electron beam.

12. The process of claim 7, wherein the densifier is an ion implantation.

13. The process of claim 7, wherein the hardened surface has a depth of 2-50 nm.

14. The process of claim 7, wherein the transforming step includes at least one of decarboxylation cross-linking, and densification of the top surface and the side surfaces to form the hardened surface.

15. An integrated circuit fabrication process, the process comprising:

patterned a feature on a photoresist layer disposed over a substrate, the feature patterned in accordance with a pattern provide on a mask or reticle and a radiation at a deep ultraviolet or extreme ultraviolet lithographic wavelength;

developing the photoresist layer, the patterned photoresist layer including at least one feature having a top surface and side surfaces;

exposing the photoresist layer to a fluorine-based or argons densifier;

transforming the top surface and the side surfaces with the densifier to form a hardened surface; and

etching the substrate in accordance with the transformed feature, wherein the exposing step occurs after the developing step and before the etching step, and an etch stability of the feature is a function of the hardened surface, wherein the transforming step includes fluorinating the top surface and the side surfaces.

16. A method of using a feature on a photoresist layer disposed above a layer or substrate, the feature including exposed surfaces, the feature being lithographically patterned using at least one of a deep ultraviolet lithographic wavelength, a vacuum ultraviolet lithographic wavelength, and an extreme ultraviolet lithographic wavelength or has a vertical thickness less than approximately 0.25 μ

m, and the method comprising;

transforming the exposed surfaces to be structurally denser than the untreated region due to at least one of a fluorination, a fluorine ion implantation and argon ion implantation; and

etching or doping the layer or substrate according to the feature, wherein the exposed surfaces are structurally denser due to the fluorination, the fluorination including the feature being exposed to a fluorine-based plasma.

17. The method of claim 16, wherein a depth of the exposed surfaces is in the range of 2-50 nm.

18. The method of claim 16, wherein the exposed surfaces comprise a top surface and side surfaces of the feature.

19. The method of claim 16, wherein the transforming step includes cross-linking.

20. The method of claim 16, wherein the fluorine-based plasma has operating parameters of 10-2000 sccm flow rate, 5-1000 mTorr chamber pressure, 50-2000 W RF power, and 20-80°

C. lower electrode temperature.

21. The feature of claim 16, wherein the material comprising the photoresist layer is an organic-based photoresist material based on at least one of phenolic polymers, acrylate polymers, and alicyclic polymers.

22. The method of claim 16, wherein the photoresist layer comprises an acrylate or alicyclic polymer and the feature is lithographically patterned using a 193 nm wavelength of radiation.

23. The method of claim 16, wherein the feature is at least one of a conducting line, a gate for a transistor device, a contact hole, a via structure, or a trench.