Method for selecting components for a matched set from a wafer-interposer assembly

• US 6,815,712 B1
• Filed: 10/02/2000
• Issued: 11/09/2004
• Est. Priority Date: 10/02/2000
• Status: Expired due to Term

• Current Assignee: Transpacific Multicast, LLC
• Original Assignee: Eaglestone Partners I LLC
• Inventors: Kline, Jerry D.
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US09/678,163
• Time in Patent Office: 1,499 Days
• Field of Search: 438/14, 438/15, 438/106, 438/107, 438/480, 438/108, 438/113, 438/615-617, 257/48, 257/686, 324/754, 324/755, 324/757
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate

Abstract

A matched set of integrated circuit chips (24) and a method for assembling such integrated circuit chips (24) into a matched set are disclosed. A semiconductor wafer (18) having a plurality of integrated circuit chips (24) is electrically and mechanically coupled to a wafer interposer (12) to form a wafer-interposer assembly (10). The integrated circuit chips (24) of the wafer (18) are then tested together by attaching the wafer-interposer assembly (10) to a testing apparatus and running the integrated circuit chips (24) through various testing sequences. The wafer-interposer assembly (10) is then diced into a plurality of chip assemblies each having a chip (24) and a section of the wafer interposer (12). Based upon the testing, the chip assemblies are sorted and at least two of the chip assemblies are selected for inclusion in the matched set.

Claims

1. A method for selecting components for a matched set comprising the steps of:

electrically and mechanically coupling a semiconductor wafer having a plurality of integrated circuit chips to an interposer to form a wafer-interposer assembly;

simultaneously testing at least two of the integrated circuit chips of the semiconductor wafer to determine inclusion in the matched set;

dicing the wafer-interposer assembly into a plurality of chip assemblies; and

selecting at least two of the chip assemblies corresponding to the at least two of the integrated circuit chips determined for inclusion in the matched set based upon the simultaneous testing.

2. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing groups of the integrated circuit chips together to identify which groups of integrated circuit chips perform best together for inclusion in a selected number of high performance matched sets.

3. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing groups of integrated circuit chips together to grade the groups of integrated circuit chips for performance such that the overall performance of matched sets assembled from the chip assemblies is maximized.

4. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing groups of the integrated circuit chips together to identify the compatibility of individual integrated circuit chips with one another.

5. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing groups of the integrated circuit chips together to identify which individual integrated circuit chips are incompatible with one another.

6. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing the at least two of the integrated circuit chips for performance over a range of temperatures.

7. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously performing burn-in testing of the at least two of the integrated circuit chips.

8. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously vibrating the at least two of the integrated circuit chips.

9. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing the at least two of the integrated circuit chips for leakage currents.

10. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing the at least two of the integrated circuit chips for offset voltages.

11. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing the at least two of the integrated circuit chips for gain tracking.

12. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing the at least two of the integrated circuit chips for bandwidth.

13. The method as recited in claim 1 wherein the step of simultaneously testing at least two of the integrated circuit chips further comprises simultaneously testing the at least two of the integrated circuit chips for speed grades.

14. The method as recited in claim 1 wherein the integrated circuit chips of the semiconductor wafer are digital devices.

15. The method as recited in claim 1 wherein the integrated circuit chips of the semiconductor wafer are analog devices.

16. The method as recited in claim 1 wherein the integrated circuit chips of the semiconductor wafer are RF devices.

17. The method as recited in claim 1 wherein the integrated circuit chips of the semiconductor wafer are mixed signal devices.

18. A matched set assembled by the method as recited in claim 1.

19. A method for assembling a matched set comprising the steps of:

providing a semiconductor wafer having a plurality of integrated circuit chips;

electrically and mechanically coupling the wafer to an interposer to form a wafer-interposer assembly;

simultaneously testing pairs of the integrated circuit chips of the wafer to determine inclusion in the matched set;

dicing the wafer-interposer assembly into a plurality of chip assemblies;

sorting the chip assemblies based upon the inclusion determinations performed during the simultaneous testing of the pairs of the integrated circuit chips; and

electrically coupling at least two of the chip assemblies corresponding to a sorted pair of the integrated circuit chip onto a substrate, thereby assembling the matched set.

20. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing groups of the integrated circuit chips together to identify which groups of integrated circuit chips perform best together for inclusion in a selected number of high performance matched sets.

21. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing groups of integrated circuit chips together to grade the groups of integrated circuit chips for performance such that the overall performance of matched sets assembled from the chip assemblies is maximized.

22. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing groups of the integrated circuit chips together to identity the compatibility of individual integrated circuit chips with one another.

23. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing groups of the integrated circuit chips together to identify which individual integrated circuit chips are incompatible with one another.

24. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing the pairs of the integrated circuit chips for performance over a range of temperatures.

25. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously performing burn-in testing of the pairs of the integrated circuit chips.

26. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously vibrating the pairs of the integrated circuit chips.

27. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing the pairs of the integrated circuit chips for leakage currents.

28. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing the pairs of the integrated circuit chips for offset voltages.

29. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing the pairs of the integrated circuit chips for gain tracking.

30. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing the pairs of the integrated circuit chips for bandwidth.

31. The method as recited in claim 19 wherein the step of simultaneously testing pairs of the integrated circuit chips further comprises simultaneously testing the pairs of the integrated circuit chips for speed grades.

32. The method as recited in claim 19 wherein the integrated circuit chips of the semiconductor wafer are digital devices.

33. The method as recited in claim 19 wherein the integrated circuit chips of the semiconductor wafer analog devices.

34. The method as recited in claim 19 wherein the integrated circuit chips of the semiconductor wafer mixed signal devices.

35. The method as recited in claim 19 wherein the integrated circuit chips of the semiconductor wafer are RF devices.

36. A matched set assembled by the method as recited in claim 19.

37. A matched set of integrated circuit chips comprising:

a first chip assembly diced from a wafer-interposer assembly, the first chip assembly including a first integrated circuit chip from a wafer;

a second chip assembly diced from the wafer-interposer assembly, the second chip assembly including a second integrated circuit chip from the wafer, the first and second integrated circuit chips being previously simultaneously tested to determine inclusion in the matched set as part of the wafer-interposer assembly,

wherein the first and second integrated circuit chips are selected from the group consisting of digital devices, analog devices, RF devices and mixed signal devices; and

a substrate on to which the first and second chip assemblies are electrically coupled.

38. The matched set as recited in claim 37 further comprising a third chip assembly diced from the wafer-interposer assembly, the third chip assembly including a third integrated circuit chip from the wafer, the first, second and third integrated circuit chips being previously simultaneously tested as part of the wafer-interposer assembly, the third chip assembly electrically coupled to the substrate.