Tft matrix for optical sensor comprising a photosensitive semiconductor layer, and optical sensor comprising such an active matrix

• US 6,815,716 B2
• Filed: 03/18/2003
• Issued: 11/09/2004
• Est. Priority Date: 09/19/2000
• Status: Expired due to Fees

• Current Assignee: Thales Avionics LCD S.A. (Thales SA)
• Original Assignee: Thales Avionics LCD S.A. (Thales SA)
• Inventors: Sanson, Eric, Szydlo, Nicolas
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/380,757
• Publication Number:
  US 20040036092A1
• Time in Patent Office: 602 Days
• Field of Search: 257/59, 257/72, 257/350, 257/532, 257/773, 257/776, 257/355, 250/370.09
• US Class Current: 257/59
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14676 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00

Abstract

The invention concerns an active TFT matrix for optical sensor comprising a substrate, a TFT transistor matrix formed on said substrate, a set of transistor control lines (3): a conductor level (4) according to a specific pattern forming an electrode array (5), each electrode (5) defining a zone called pixel: a set of columns (10) for load transfer between the electrodes (5) and an external electronics. The pixel electrode (5) is located entirely inside an outline delimited by two lines (3) and two successive columns (10), a protective gap (g1, g2) being provided between the inside edge of said outline and the periphery of the pixel (5) such that the pixel electrode (5) does not cover either the lines (3) or the columns (10).

Claims

1. A TFT active matrix for an optical sensor comprising:

a substrate;

a matrix of TFT transistors formed on this substrate, each transistor comprising a gate, a source and a drain;

a set of row lines for controlling the TFT transistors by means of their gates, this set of row lines being placed on the substrate;

a conducting level in a particular pattern forming a matrix of electrodes, each electrode defining a zone called a pixel;

a set of column lines making it possible to transfer charge through the transistors between the electrodes and external electronics, the column lines being connected to the sources of the TFT transistors;

an insulating layer between the electrodes and the column lines, this insulating layer being open locally over each pixel in order to put the pixel electrode in contact with the drain of the transistor;

a photosensitive semiconducting layer in contact with the pixel electrodes in order to convert the electromagnetic radiation into electric charges collected by the electrodes,

a set of storage row lines forming capacitors with the pixel electrodes or drains,

and connections, forming bridges, provided in order to electrically connect the successive storage row lines and to make it possible, when controlling a row of pixels, to distribute the removal of charges from the entire row of pixels over several parallel storage row lines,

wherein the storage row lines are provided in a level located on the substrate below the level of the control row lines and a thin insulating level is located between the level of the storage row lines and the level of the control row lines.

2. The matrix as claimed in claim 1, wherein the storage row lines are parallel to the control row lines, the connections being parallel to the column lines.

3. The matrix as claimed in claim 1, wherein, the storage row lines form a capacitor with a specific electrode made in the same level as the control row lines and electrically connected to the pixel electrode.

4. The matrix as claimed in claim 1, wherein connections are parallel to the column lines and at the same level as the column lines.

5. The matrix as claimed in claim 1, wherein, the connections are parallel to the column lines and in equal numbers.

6. The matrix as claimed in claim 1, wherein the connections are parallel to the column lines, and less numerous.

7. The matrix as claimed in claim 6, comprising one connection parallel to the column lines every sixteen column lines.

8. The matrix as claimed in claim 1, wherein, high-capacitance zones defined by the stack of three layers formed with the storage row line level placed on the substrate, the thin insulator level, and an upper conducting level, said stack defining planar capacitors in which the thin insulator level is never used alone in order to electrically separate a step of the storage row line level from the upper conducting level.

9. The matrix as claimed in claim 1, comprising a device for protecting the pixel against voltages which are too high.

10. An optical sensor, in particular for X-rays, comprising a matrix as claimed in claim 1.