Method for selective trimming of gate structures and apparatus formed thereby
First Claim
1. An electrical structure, comprising:
- a semiconductor substrate having an electrically insulative isolation structure therein, wherein a top surface of the substrate and a top surface of the isolation structure are coplanar;
a first gate oxide layer on the substrate and in direct mechanical contact with the top surface of the substrate;
a first polysilicon layer on the first gate oxide layer and in direct mechanical contact with the first gate oxide layer;
a second gate oxide layer on the isolation structure and in direct mechanical contact with the top surface or the isolation structure, wherein the first and second gate oxide layers have a same thickness in a first direction perpendicular to the top surface of the substrate, and wherein the first gate oxide layer has a smaller width than the second gate oxide layer in a second direction parallel to the top surface of the substrate; and
a second polysilicon layer on the second gate oxide layer and in direct mechanical contact with the second gate oxide layer, wherein the first polysilicon layer has a smaller thickness than the second polysilicon layer in the first direction, and wherein the first polysilicon layer has a smaller width than the second polysilicon layer in the second direction.
0 Assignments
0 Petitions
Accused Products
Abstract
A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.
-
Citations
17 Claims
-
1. An electrical structure, comprising:
-
a semiconductor substrate having an electrically insulative isolation structure therein, wherein a top surface of the substrate and a top surface of the isolation structure are coplanar;
a first gate oxide layer on the substrate and in direct mechanical contact with the top surface of the substrate;
a first polysilicon layer on the first gate oxide layer and in direct mechanical contact with the first gate oxide layer;
a second gate oxide layer on the isolation structure and in direct mechanical contact with the top surface or the isolation structure, wherein the first and second gate oxide layers have a same thickness in a first direction perpendicular to the top surface of the substrate, and wherein the first gate oxide layer has a smaller width than the second gate oxide layer in a second direction parallel to the top surface of the substrate; and
a second polysilicon layer on the second gate oxide layer and in direct mechanical contact with the second gate oxide layer, wherein the first polysilicon layer has a smaller thickness than the second polysilicon layer in the first direction, and wherein the first polysilicon layer has a smaller width than the second polysilicon layer in the second direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A structure comprising:
-
a semiconductor substrate;
a first gate oxide layer on the substrate and in direct mechanical contact with the top surface of the substrate;
a first polysilicon layer on the first gate oxide layer and in direct mechanical contact with the first gate oxide layer;
an electrically insulative isolation structure within the substrate, wherein the top surface of the substrate and a top surface of the insulation structure are coplanar;
a second gate oxide layer on the isolation structure and in direct mechanical contact with the top surface of the isolation structure; and
a second polysilicon layer on the second gate oxide layer and in direct mechanical contact with the second gate oxide layer, wherein the first polysilicon layer has a smaller thickness than the second polysilicon layer in a first direction perpendicular to the top surface of the substrate, and wherein the first polysilicon layer has a smaller width than the second polysilicon layer in a second direction parallel to the top surface of the substrate.
-
Specification