Field effect transistor with channel extending through layers on a substrate

• US 6,815,750 B1
• Filed: 05/22/2002
• Issued: 11/09/2004
• Est. Priority Date: 05/22/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kamins, Theodore I.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): MAGEE, THOMAS J
• Application Number:
  US10/155,416
• Time in Patent Office: 902 Days
• Field of Search: 257/302, 257/412, 257/382, 257/383, 257/334, 438/230, 438/251, 428/357, 428/364
• US Class Current: 257/302
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field effect transistor (FET) has a channel formed in a pore extending up from a conductive portion of a substrate through a stack of planar layers including a first insulating layer, a gate layer, and a second insulating layer. The pore can be upright or inclined relative to the layers. A nanoparticle used for a mask of a directional etching process ultimately defines the size of the pore and therefore the channel width. The substrate or a doped region of the substrate formed immediately beneath the channel can be a source/drain of the FET with the other drain/source being a doped region adjacent the top of the channel. The gate layer can form the gate or can contact a separate gate inside the pore.

Claims

1. A field effect transistor comprising, in combination:

a) a substrate having a substantially-planar upper substrate surface;

b) an elongated channel of semiconductor material;

c) said channel including a top and a bottom with the bottom of the channel contacting said upper substrate surface;

d) said substrate being substantially conductive in the region contacting said bottom of said elongated channel;

e) said channel including a heavily doped region adjacent the top thereof; and

f) a gate comprising a planar layer of conductive material arranged substantially parallel to said upper substrate surface, wherein the planar layer comprises a pore through which the elongated channel extends.

2. A field effect transistor as defined in claim 1 further including a gate insulator layer substantially surrounding the length of said elongated channel.

3. A field effect transistor as defined in claim 1 further including a first substantially-planar insulating layer between said gate and said upper substrate surface.

4. A field effect transistor as defined in claim 3 further including a second substantially-planar insulating layer overlying said gate.

5. A field effect transistor as defined in claim 2 further including a layer of conductive material in contact with said gate and substantially surrounding the length of said elongated channel.

6. A field effect transistor as defined in claim 1 wherein said substrate is of semiconductor material.

7. A field effect transistor as defined in claim 6 wherein said semiconductor material is globally moderately-doped and includes a locally highly-doped region adjacent the bottom of said elongated channel.

8. A field effect transistor as defined in claim 6 wherein said semiconductor material is globally heavily-doped.

9. A field effect transistor as defined in claim 1 wherein said elongated channel comprises silicon.

10. A field effect transistor as defined in claim 1 further characterized in that:

a) said substrate comprises single crystal silicon; and

b) said elongated channel comprises silicon epitaxially grown from said substrate.

14. A field effect transistor as defined in claim 1, wherein said pore is a nanopore.

15. A field effect transistor as defined in claim 4, wherein said pore extends through said first substantially-planar insulating layer and said second substantially-planar insulating layer.

16. A field effect transistor as defined in claim 15, further including a gate insulator layer that substantially surrounds said elongated channel and resides between said gate and said elongated channel in said pore.

17. A field effect transistor as defined in claim 16, further including a layer of conductive material that is within said pore, in contact with said gate, and substantially surrounds the length of said elongated channel.

11. A transistor comprising:

a substrate;

a first insulating layer overlying the substrate;

a substantially-planar conductive layer overlying the first insulating layer;

a second insulating layer overlying the conductive layer, wherein a pore extends through the second insulating layer, the conductive layer, and the first insulating layer to the substrate; and

a gate insulator and a channel in the pore, the gate insulator insulating the channel from the substantially-planar conductive layer, wherein;

a first terminal of the transistor resides in the substrate and contacts a bottom of the channel;

a second terminal of the transistor resides at top of the channel; and

a gate of the transistor comprises an edge of the substantially-planar conductive layer surrounding the pore.

12. The transistor of claim 11, wherein a length of the gate is equal to a thickness of the substantially-planar conductive layer.

13. The transistor of claim 11, wherein the channel is substantially orthogonal to an upper surface of the substrate.