Structure for scalable, low-cost polysilicon DRAM in a planar capacitor

• US 6,815,751 B2
• Filed: 07/01/2002
• Issued: 11/09/2004
• Est. Priority Date: 07/01/2002
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Mann, Randy W., Brown, Jeffrey S.
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US10/064,301
• Publication Number:
  US 20040000685A1
• Time in Patent Office: 862 Days
• Field of Search: 257/301-305
• US Class Current: 257/305
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

Claims

1. A structure formed on a semiconductor, substrate comprising:

a plurality of isolation filled trenches in a first region of the substrate;

at least two adjacent memory cells comprising a plurality of holes in the substrate, each of said holes having a plurality of sidewalls and a bottom wall, said adjacent memory cells located in a second region of the semiconductor substrate in which said plurality of isolation filled trenches are absent, said holes having a depth proximate that of said plurality of isolation filled trenches;

insulating material present in each of said plurality of holes on said plurality of sidewalls and bottom wall; and

a conductor overfilling each of said holes and extending onto an adjacent upper surface of the substrate;

wherein said adjacent memory cells are electrically isolated by said plurality of holes.

2. The structure of claim 1 further comprising counter-doped regions present in pillar areas of said semiconductor substrate that surround said holes.

3. The structure of claim 1 further comprising well implants regions located in said semiconductor substrate.

4. The structure of claim 1 further comprising at least one transfer device located atop a surface of said semiconductor substrate adjoining said plurality of holes.

5. The structure of claim 4 wherein said at least one transfer device is a field effect transistor.

6. The structure of claim 2, wherein said insulating material is thicker on said bottom walls of said plurality of holes than on said plurality of sidewalls of said plurality of holes.

7. The structure of claim 6, wherein said insulating material is disposed on said upper surface of the substrate beneath portions of said conductor thereon.

8. The structure of claim 1, wherein said holes have a depth greater than said plurality of isolation-filled trenches.

9. The structure of claim 8, wherein an isolation dopant region is disposed below said bottom walls of said plurality of holes.

10. The structure of claim 1, wherein the substrate has a buried insulation region, and wherein said plurality of holes extend into said buried insulation region.