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Structure for scalable, low-cost polysilicon DRAM in a planar capacitor

  • US 6,815,751 B2
  • Filed: 07/01/2002
  • Issued: 11/09/2004
  • Est. Priority Date: 07/01/2002
  • Status: Expired due to Fees
First Claim
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1. A structure formed on a semiconductor, substrate comprising:

  • a plurality of isolation filled trenches in a first region of the substrate;

    at least two adjacent memory cells comprising a plurality of holes in the substrate, each of said holes having a plurality of sidewalls and a bottom wall, said adjacent memory cells located in a second region of the semiconductor substrate in which said plurality of isolation filled trenches are absent, said holes having a depth proximate that of said plurality of isolation filled trenches;

    insulating material present in each of said plurality of holes on said plurality of sidewalls and bottom wall; and

    a conductor overfilling each of said holes and extending onto an adjacent upper surface of the substrate;

    wherein said adjacent memory cells are electrically isolated by said plurality of holes.

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