Inverted staggered thin film transistor with salicided source/drain structures and method of making same

• US 6,815,781 B2
• Filed: 10/15/2002
• Issued: 11/09/2004
• Est. Priority Date: 09/25/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Petti, Christopher J., Herner, S. Brad, Walker, Andrew J., Vyvoda, Michael A.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US10/270,394
• Publication Number:
  US 20040036124A1
• Time in Patent Office: 756 Days
• Field of Search: 257/67, 257/72, 257/133, 257/382, 257/377, 257/383, 257/384, 257/385, 257/388, 257/59, 257/135, 257/132, 257/58, 257/122, 257/315, 257/316, 257/66, 257/390, 349/58, 349/122
• US Class Current: 257/377
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.

Claims

1. A semiconductor device, comprising:

a gate electrode;

a gate insulating layer located above the gate electrode;

an active layer located above the gate insulating layer;

an insulating fill layer located above the active layer;

a first opening and a second opening located in the insulating fill layer;

a first source or drain electrode located in the first opening;

a second source or drain electrode located in the second opening; and

wherein at least one of the first and the second source or drain electrodes comprises a polysilicon layer and a metal silicide layer.

2. The device of claim 1, wherein the gate insulating layer comprises a portion of a charge storage region.

3. The device of claim 1, wherein a top surface of the first source or drain electrode and a top surface of the second source or drain electrode are substantially coplanar with a top surface of the insulating fill layer.

4. The device of claim 3, wherein the metal silicide layer is located in contact with the active layer and the polysilicon layer is located above the metal silicide layer.

5. The device of claim 3, wherein the polysilicon layer is located in contact with the active layer and the metal silicide layer is located above the polysilicon layer.

6. The device of claim 3, wherein the metal silicide layer is located between the polysilicon layer and a second polysilicon layer.

7. The device of claim 3, wherein:

the metal silicide layer is located in contact with the active layer;

the polysilicon layer is located above the metal silicide layer; and

a second metal silicide layer is located above the polysilicon layer in the at least one source and drain electrode.

8. The device of claim 1, wherein:

transistor source and drain regions are located in the active layer, the source region contacting the first source or drain electrode and the drain region contacting the second source or drain electrode;

a transistor channel region is located in the active layer between the first and second source and drain regions and below the insulating fill layer; and

the gate insulating layer comprises a portion of a charge storage region.

9. The device of claim 8, wherein:

the charge storage region comprises;

a dielectric isolated floating gate;

an insulating layer containing conductive nanocrystals;

or

a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking dielectric layer;

the active layer comprises a polysilicon active layer;

the insulating fill layer comprises silicon dioxide; and

the metal silicide layer comprises a titanium silicide layer, a cobalt silicide layer or a nickel silicide layer.

10. The device of claim 9, further comprising:

a plurality of gate lines located at a first height and extending in a first direction;

a plurality of source and drain lines located at a second height above the first height and extending in a second direction different from the first direction; and

a plurality of charge storage regions and active layers located between the plurality of gate lines and the plurality of source and drain lines, such that a plurality of first inverted staggered thin film transistors are located at intersections of the gate lines and the source and drain lines in a first device level.

11. The device of claim 10, further comprising at least one subsequent device level monolithically formed above the first device level, wherein the at least one subsequent device level comprises a plurality of second thin film transistors.

12. A monolithic, three dimensional array of thin film transistors, comprising:

a substrate;

an intermediate dielectric layer located above the substrate;

a first planarized insulating fill layer located at a first height above the intermediate dielectric layer;

a first plurality of openings located in the first planarized insulating fill layer;

a plurality of first word lines located in the first plurality of openings in the first planarized insulating fill layer and extending in a first direction;

a first gate insulating layer located above the first word lines and above the first insulating fill layer;

a first active layer located above the first gate insulating layer;

a second insulating fill layer located above the first active layer;

a second plurality of openings located in the second insulating fill layer;

first bit lines located in the second plurality of openings in the second insulating fill layer, wherein at least one of the first bit lines comprises a first polysilicon layer and a first metal suicide layer, and the first bit lines extend in a second direction different from the first direction;

a second active layer located above the first bit lines and above the second insulating fill layer;

a second gate insulating layer located above the second active layer; and

a plurality of second word lines located above the second gate insulating layer, the second word lines extending in the first direction.

13. The array of claim 12, wherein:

the first gate insulating layer comprises a portion of a first charge storage region;

the second gate insulating layer comprises a portion of a second charge storage region; and

top surfaces of the first bit lines are substantially coplanar with a top surface of the second insulating fill layer.

14. The array of claim 13, wherein the first metal silicide layer is located in contact with the first active layer and the first polysilicon layer is located above the first metal silicide layer and in contact with the second active layer.

15. The array of claim 13, wherein the first polysilicon layer is located in contact with the first active layer and the first metal silicide layer is located above the first polysilicon layer and in contact with the second active layer.

16. The array of claim 13, wherein the first metal suicide layer is located between the first polysilicon layer and a second polysilicon layer.

17. The array of claim 13, wherein:

the first metal silicide layer is located in contact with the first active layer;

the first polysilicon layer is located above the first metal silicide layer; and

a second metal silicide layer is located above the polysilicon layer in the at least one of the first bit lines.

18. The array of claim 13, further comprising:

first transistor source and drain regions located in the first active layer in contact with the first bit lines;

second transistor source and drain regions located in the second active layer in contact with the first bit lines;

first transistor channel regions located in the first active layer alternating with the first source and drain regions;

second transistor channel regions located in the second active layer alternating with the second source and drain regions;

a third planarized insulating fill layer;

a third plurality of openings in the third planarized insulating fill layer, wherein the second word lines are located in the third plurality of openings;

a third charge storage region located on the second word lines and the third insulating fill layer;

a third active layer located on the third charge storage region;

a fourth insulating fill layer located above the third active layer;

a fourth plurality of openings located in the fourth insulating fill layer; and

second bit lines located in the fourth plurality of openings in the fourth insulating fill layer, wherein the second bit lines comprise a second polysilicon layer and a second metal silicide layer, and the second bit lines extend in the second direction.

19. The array of claim 18, wherein:

at least one of the first word lines comprise a metal silicide layer located between two first word line heavily doped polysilicon layers;

at least one of the second word lines comprise a metal silicide layer located between two second word line heavily doped polysilicon layers;

the first, second and third charge storage regions are selected from a group consisting of;

a dielectric isolated floating gate;

an insulating layer containing conductive nanocrystals; and

a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking dielectric;

the first, second and third active layers comprise polysilicon active layers; and

the first and second source and drain regions comprise heavily doped polysilicon regions.

20. A method of making a semiconductor device, comprising:

forming a first gate line layer, patterning the first gate line layer to form a plurality of first gate lines, wherein at least one gate electrode is provided in the plurality of first gate lines;

forming a first insulating fill layer over and between the first gate lines;

planarizing the first fill layer coplanar with top surfaces of the first gate lines;

forming a first gate insulating layer over the first gate lines and the first fill layer;

forming a first active layer over the first gate insulating layer, forming a second insulating fill layer over the first active layer;

patterning the second insulating fill layer such that first portions of the first active layer are covered by the second insulating fill layer and openings in the second insulating fill layer expose second portions of the first active layer;

forming a first source/drain line film comprising a first polysilicon layer and a first metal silicide layer in the openings in the second insulating fill layer; and

planarizing the first source/drain line film such that first source and drain electrodes remain in the openings in the second insulating fill layer, and top surfaces of the first source and drain electrodes are coplanar with a top surface of the second insulating fill layer;

wherein the first source and drain electrodes in the completed semiconductor device comprise the first polysilicon layer and the first metal silicide layer.

21. The method of claim 20, wherein:

the first gate lines comprise a heavily doped polysilicon layer over a metal silicide layer;

the first insulating fill layer comprises a chemically mechanically polished silicon dioxide layer;

the second insulating fill layer comprises a silicon dioxide layer;

the first gate insulating layer comprises a portion of a charge storage region selected from a group consisting of;

a dielectric isolated floating gate;

an insulating layer containing conductive nanocrystals; and

a composite dielectric film comprising a tunneling layer, a charge storage layer and a blocking oxide; and

the first active layer comprises a polysilicon active layer.

22. The method of claim 20, wherein the steps of planarizing comprise chemical mechanical polishing.

23. The method of claim 22, wherein forming the first source/drain line film comprises forming the first polysilicon layer in the openings in the second insulating fill layer, such that the first polysilicon layer does not completely fill the openings, forming the first metal silicide layer on the first polysilicon layer, and forming a second polysilicon layer on the first metal silicide layer in the openings and over the second insulating fill layer.

24. The method of claim 22, wherein forming the first source/drain line film comprises forming the first polysilicon layer in the openings in the second insulating fill layer and over the second insulating fill layer, selectively etching back the first polysilicon layer such that the first polysilicon layer does not completely fill the openings, forming the first metal silicide layer on the first polysilicon layer, and forming a second polysilicon layer on the first metal silicide layer in the openings and over the second insulating fill layer.

25. The method of claim 22, further comprising implanting source and drain regions in the first active layer through the openings in the second insulating fill layer.

26. The method of claim 22, wherein forming the first source/drain line film comprises forming the first metal silicide layer in contact with the first active layer and forming the first polysilicon layer on the first metal silicide layer.

27. The method of claim 26, further comprising forming a second metal silicide layer on the first polysilicon layer.

28. The method of claim 22, wherein forming the first source/drain line film comprises forming the first polysilicon layer located in contact with the first active layer and selectively forming the first metal silicide layer on the first polysilicon layer after the step of planarizing the first source/drain line film.

29. The method of claim 28, further comprising annealing the first polysilicon layer to outdiffuse source and drain dopants from the first polysilicon layer into the first active layer.

30. The method of claim 22, further comprising:

depositing a second active layer over the first source and drain electrodes and over the second fill layer;

outdiffusing source and drain dopants from the first source and drain electrodes into the second active layer;

forming a second gate insulating layer over the second active layer; and

forming second gate lines over the second gate insulating layer.

31. The method of claim 30, further comprising:

forming a third insulating fill layer over and between the second gate lines;

planarizing the third fill layer coplanar with top surfaces of the second gate lines;

forming a third gate insulating layer over the second gate lines and the third fill layer;

forming a third active layer over the third gate insulating layer;

forming a fourth insulating fill layer over the third active layer;

selectively patterning the fourth insulating fill layer such that first portions of the third active layer are covered by the fourth insulating fill layer and openings in the second insulating fill layer expose second portions of the third active layer;

forming a second source/drain line film over the fourth patterned insulating fill layer and in the openings in the fourth patterned insulating fill layer; and

planarizing the second source/drain line film such that second source and drain electrodes remain in the openings in the fourth patterned insulating fill layer and top surfaces of the second source and drain electrodes are coplanar with a top surface of the fourth insulating fill layer.

32. A method of making an inverted staggered thin film transistor, comprising:

forming a gate electrode;

forming a gate insulating layer over the gate electrode;

forming an active layer over the gate insulating layer;

forming an insulating fill layer over the active layer;

patterning the insulating fill layer such that first portions of the active layer are covered by the insulating fill layer and first and second openings in the insulating fill layer expose second portions of the active layer;

forming a source/drain line film comprising a first polysilicon layer and a metal silicide layer in the first and second openings in the insulating fill layer; and

planarizing the source/drain line film such that a first source or drain electrode remains in the first opening and a second source or drain electrode remains in the second opening in the insulating fill layer, and top surfaces of the first and second source or drain electrodes are coplanar with a top surface of the insulating fill layer;

wherein the first and the second source or drain electrodes in the completed inverted staggered thin film transistor comprise the first polysilicon layer and the first metal silicide layer.

33. The method of claim 32, wherein forming the source/drain line film comprises forming the first polysilicon layer located in contact with the active layer and selectively forming the metal silicide layer on the first polysilicon layer after the step of planarizing the source/drain line film.

34. The method of claim 32, wherein forming the source/drain line film comprises forming the first polysilicon layer in the openings in the insulating fill layer and over the insulating fill layer, selectively etching back the first polysilicon layer such that the first polysilicon layer does not completely fill the openings, forming the metal silicide layer on the first polysilicon layer, and forming a second polysilicon layer on the metal silicide layer in the openings and over the insulating fill layer.

35. The method of claim 32, further comprising implanting source and drain regions in the active layer through the openings in the insulating fill layer.

36. The method of claim 32, further comprising:

forming the first polysilicon layer in contact with the active layer; and

annealing the first polysilicon layer to outdiffuse source and drain dopants from the first polysilicon layer into the active layer.

37. The method of claim 32, further comprising:

forming a second active layer on the first polysilicon layer; and

annealing the first polysilicon layer to outdiffuse source and drain dopants from the first polysilicon layer into the second active layer.

38. The method of claim 32, further comprising:

forming the metal suicide layer over the first polysilicon layer;

implanting dopants into the metal silicide layer;

forming a second active layer on the metal silicide layer; and

annealing the metal silicide layer to outdiffuse source and drain dopants from the metal silicide layer into the second active layer.

39. The method of claim 32, wherein forming the source/drain line film comprises forming the metal silicide layer in contact with the active layer and forming the first polysilicon layer on the metal silicide layer.

40. The method of claim 39, further comprising forming a second metal silicide layer on the first polysilicon layer.