Reduced terminal testing system

• US 6,815,968 B2
• Filed: 08/05/2002
• Issued: 11/09/2004
• Est. Priority Date: 09/13/1996
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J., Farnworth, Warren M., Cloud, Eugene H., Nevill, Leland R.
• Primary Examiner(s): Kang, Donghee
• Application Number:
  US10/212,899
• Publication Number:
  US 20030003606A1
• Time in Patent Office: 827 Days
• Field of Search: 324/754, 324/755, 324/758, 324/763, 324/765
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2841 Signal generators
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2868 Complete testing stations; systems; procedures; software aspects
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer.

Claims

1. A method of testing for a semiconductor die, comprising:

providing a semiconductor die having a bond pad having circuitry connected thereto on a substrate;

providing a power signal having an alternating signal having a predetermined characteristic superimposed thereon to the semiconductor die using the bond pad;

subjecting the semiconductor die to the alternating signal having the predetermined characteristic superimposed on the power signal; and

placing the semiconductor die into a mode when the circuitry connected thereto receives the alternating signal having the predetermined characteristic.

2. The method of claim 1, wherein the alternating signal comprises a substantially continuous digital signal.

3. The method of claim 1, wherein the alternating signal comprises a discontinuous digital signal.

4. The method of claim 1, wherein the alternating signal comprises a continuous analog signal.

5. The method of claim 1, wherein the alternating signal comprises a discontinuous analog signal.

6. The method of claim 1, wherein the alternating signal comprises a frequency modulated signal.

7. The method of claim 1, wherein the alternating signal comprises an amplitude modulated signal.

8. The method of claim 1, wherein the alternating signal comprises a phase shift keying modulated signal.

9. The method of claim 1, wherein the alternating signal comprises a pulse width modulated signal.

10. The method of claim 1, wherein the alternating signal comprises a quadrature phase shift keying modulated signal.

11. A method of testing for a semiconductor die comprising:

providing a semiconductor die having a bond pad having circuitry connected thereto on a substrate; and

providing an alternating signal having a predetermined characteristic to the semiconductor die superimposed on a power signal using the bond pad of the semiconductor die; and

placing the semiconductor die into a mode when the circuitry connected thereto receives the alternating signal having the predetermined characteristic, the alternating signal comprising at least one of a continuous digital signal, a discontinuous digital signal, a continuous analog signal, a discontinuous analog signal, a frequency modulated signal, an amplitude modulated signal, a phase shift keying modulated signal, a pulse width modulated signal, and quadrature phase shift keying modulated signal.