Inspection method and inspection device for active matrix substrate, inspection program used therefor, and information storage medium

• US 6,815,975 B2
• Filed: 05/20/2003
• Issued: 11/09/2004
• Est. Priority Date: 05/21/2002
• Status: Expired due to Fees

• Current Assignee: Wintest Corp. (Wuhan Jingce Electronic Group Co., Ltd.)
• Original Assignee: Wintest Corp. (Wuhan Jingce Electronic Group Co., Ltd.)
• Inventors: Jiang, Hui, Yamamoto, Wataru, Nara, Shoji
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/441,951
• Publication Number:
  US 20040008053A1
• Time in Patent Office: 539 Days
• Field of Search: 324/770, 324/753, 324/763-765, 324/768-769, 324/158.1, 345/3, 345/50, 345/87, 345/98, 345/100
• US Class Current: 324/760.02
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: H05B 45/60 Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

An inspection method and device are provided. The inspection method includes charging a parasitic capacitor between the gate and the drain of an operating transistor by supplying a potential from an inspection device, measuring discharge current from the parasitic capacitor by using the inspection device by discharging the parasitic capacitor, and determining whether or not a defect exists in each of a plurality of pixels by using the inspection device based on a value of the discharge current.

Claims

1. An inspection method for an active matrix substrate comprising:

a first step of providing an active matrix substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of voltage supply lines, and a plurality of pixels, each of the plurality of pixels being connected with one of the signal lines, one of the scanning lines, and one of the voltage supply lines, each of the plurality of pixels including a pixel select transistor connected with the one signal line and the one scanning line and an operating transistor, a gate of the operating transistor being connected with the pixel select transistor, one of a source and a drain of the operating transistor being connected with the one voltage supply line, and the other of the source and the drain of the operating transistor being in an open state;

a second step of charging a parasitic capacitor between the gate of the operating transistor and the one voltage supply line by supplying a potential from an inspection device;

a third step of measuring discharge current by using the inspection device when discharging the parasitic capacitor; and

a fourth step of determining whether or not a defect exists in each of the plurality of pixels by using the inspection device based on a value of the discharge current.

2. The inspection method as defined in claim 1,

wherein each of the plurality of pixels further includes a storage capacitor connected with the gate of the operating transistor, and

wherein an influence of the storage capacitor is canceled in the second step and the third step.

3. The inspection method as defined in claim 2,

wherein a potential difference between opposite ends of the storage capacitor is substantially the same in the second step and the third step.

4. The inspection method as defined in claim 1,

wherein a range of capacitance values of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line has a high-saturation region, a low-saturation region, and a transition region between the high-saturation region and the low-saturation region in which a capacitance value changes depending on an applied voltage, and

wherein a voltage is applied between the gate of the operating transistor and the one voltage supply line in at least one of the second step and the third step, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the high-saturation region.

5. The inspection method as defined in claim 1,

wherein a set of steps consisting of the second to fourth steps is performed a plurality of times while changing a voltage applied between the gate of the operating transistor and the one voltage supply line.

6. The inspection method as defined in claim 5,

wherein a range of capacitance values of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line has a high-saturation region, a low-saturation region, and a transition region between the high-saturation region and the low-saturation region in which a capacitance value changes depending on an applied voltage, and

wherein a voltage is applied between the gate of the operating transistor and the one voltage supply line in at least one of the second step and the third step performed in the set, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the transition region.

7. The inspection method as defined in claim 5,

wherein a range of capacitance values of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line has a high-saturation region, a low-saturation region, and a transition region between the high-saturation region and the low-saturation region in which a capacitance value changes depending on an applied voltage,

wherein a voltage is applied between the gate of the operating transistor and the one voltage supply line in at least one of the second step and the third step in an initial performance of the set, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the high-saturation region, and

wherein a voltage is applied between the gate of the operating transistor and the one voltage supply line in at least one of the second step and the third step in the set performed after the initial performance of the set, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the transition region.

8. The inspection method as defined in claim 7,

wherein a pixel which is determined to be normal in the fourth step in the initial performance of the set is determined in the fourth step in the set performed after the initial performance of the set.

9. The inspection method as defined in claim 1,

wherein a charge operation is performed for pixels arranged in line among the plurality of pixels by sequentially setting the scanning lines at an active potential in the second step, the pixels arranged in line being connected with each of the scanning lines, and

wherein, when all the plurality of pixels have been charged, a discharge operation is performed for the pixels arranged in line connected with each of the scanning lines by sequentially setting the scanning lines at the active potential in the third step.

10. The inspection method as defined in claim 9,

wherein the pixels arranged in line are driven by a point-at-a-time scanning by sequentially connecting the signal lines connected with the pixels arranged in line with the inspection device in the second step and the third step.

11. The inspection method as defined in claim 9,

wherein a vertical driver circuit which selectively drives the scanning lines and a horizontal driver circuit which selectively drives the signal lines are provided on the active matrix substrate, and

wherein the plurality of pixels are driven based on functions of the vertical driver circuit and the horizontal driver circuit in the second step and the third step.

12. An inspection method for an active matrix substrate comprising:

a first step of providing an active matrix substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of voltage supply lines, and a plurality of pixels, each of the plurality of pixels being connected with one of the signal lines, one of the scanning lines, and one of the voltage supply lines, each of the plurality of pixels including a pixel select transistor connected with the one signal line and the one scanning line, an operating transistor, and a storage capacitor, a gate of the operating transistor being connected with the storage capacitor and the pixel select transistor, one of a source and a drain of the operating transistor being connected with the one voltage supply line, and the other of the source and the drain of the operating transistor being in an open state;

a second step of charging the storage capacitor by supplying a potential from an inspection device;

a third step of measuring discharge current from the storage capacitor by using the inspection device when discharging the storage capacitor; and

a fourth step of determining whether or not a defect exists in each of the plurality of pixels by using the inspection device based on a value of the discharge current,

wherein an influence of a parasitic capacitor between the gate of the operating transistor and the one voltage supply line is canceled in the second step and the third step.

13. The inspection method as defined in claim 12,

wherein a potential difference between the gate of the operating transistor and the one voltage supply line is substantially the same in the second step and the third step.

14. The inspection method as defined in claim 13,

wherein a range of capacitance values of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line has a high-saturation region, a low-saturation region, and a transition region between the high-saturation region and the low-saturation region in which a capacitance value changes depending on an applied voltage, and

wherein a voltage is applied between the gate of the operating transistor and the one voltage supply line in the second step and the third step, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the low-saturation region.

15. The inspection method as defined in claim 12,

wherein a charge operation is performed for pixels arranged in line among the plurality of pixels by sequentially setting the scanning lines at an active potential in the second step, the pixels arranged in line being connected with each of the scanning lines, and

wherein, when all the plurality of pixels have been charged, a discharge operation is performed for the pixels arranged in line connected with each of the scanning lines by sequentially setting the scanning lines at the active potential in the third step.

16. The inspection method as defined in claim 15,

wherein the pixels arranged in line are driven by a point-at-a-time scanning by sequentially connecting the signal lines connected with the pixels arranged in line with the inspection device in the second step and the third step.

17. The inspection method as defined in claim 15,

wherein a vertical driver circuit which selectively drives the scanning lines and a horizontal driver circuit which selectively drives the signal lines are provided on the active matrix substrate, and

wherein the plurality of pixels are driven based on functions of the vertical driver circuit and the horizontal driver circuit in the second step and the third step.

18. An inspection device for an active matrix substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of voltage supply lines, and a plurality of pixels, each of the plurality of pixels being connected with one of the signal lines, one of the scanning lines, and one of the voltage supply lines, each of the plurality of pixels including a pixel select transistor connected with the one signal line and the one scanning line and an operating transistor, a gate of the operating transistor being connected with the pixel select transistor, one of a source and a drain of the operating transistor being connected with the one voltage supply line, and the other of the source and the drain of the operating transistor being in an open state, the inspection device comprising:

an inspection potential generating circuit which generates inspection potentials supplied to the scanning lines and the voltage supply lines;

a charge-sense circuit connected with the signal lines;

a timing signal generating circuit which generates a timing signal for driving the scanning lines, the signal lines, and the voltage supply lines; and

a determining circuit which determines whether or not a defect exists in each of the plurality of pixels based on an output from the charge-sense circuit,

wherein the inspection potential generating circuit and the charge-sense circuit supply potentials to charge a parasitic capacitor between the gate of the operating transistor and the one voltage supply line in a charging period, supply potentials to discharge the parasitic capacitor in a sensing period, and measure discharge current from the parasitic capacitor by using the charge-sense circuit in the sensing period.

19. The inspection device as defined in claim 18,

wherein the active matrix substrate further includes a plurality of common lines, each of the plurality of pixels further including a storage capacitor connected between the gate of the operating transistor and one of the common lines,

wherein the inspection potential generating circuit supplies an inspection potential also to the common lines, and

wherein the inspection potential generating circuit and the charge-sense circuit supply potentials, so that a potential difference between opposite ends of the storage capacitor is substantially the same both in the charging period and the sensing period.

20. The inspection device as defined in claim 18,

wherein a range of capacitance values of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line has a high-saturation region, a low-saturation region, and a transition region between the high-saturation region and the low-saturation region in which a capacitance value changes depending on an applied voltage, and

wherein the inspection potential generating circuit and the charge-sense circuit apply a voltage between the gate of the operating transistor and the one voltage supply line in at least one of the charging period and the sensing period, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the high-saturation region.

21. The inspection device as defined in claim 18,

wherein a range of capacitance values of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line has a high-saturation region, a low-saturation region, and a transition region between the high-saturation region and the low-saturation region in which a capacitance value changes depending on an applied voltage, and

wherein the inspection potential generating circuit and the charge-sense circuit apply a voltage between the gate of the operating transistor and the one voltage supply line in at least one of the charging period and the sensing period, so that a capacitance value of the parasitic capacitor between the gate of the operating transistor and the one voltage supply line is within the transition region.

22. The inspection device as defined in claim 18,

wherein a vertical driver circuit which selectively drives the scanning lines and a horizontal driver circuit which selectively drives the signal lines are provided on the active matrix substrate, and

wherein the timing signal generating circuit supplies a timing signal to the vertical driver circuit and the horizontal driver circuit to make a charge operation and a sense operation to be performed based on functions of the vertical driver circuit and the horizontal driver circuit.

23. An inspection device for an active matrix substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of voltage supply lines, and a plurality of pixels, each of the plurality of pixels being connected with one of the signal lines, one of the scanning lines, and one of the voltage supply lines, each of the plurality of pixels including a pixel select transistor connected with the one signal line and the one scanning line, an operating transistor, and a storage capacitor, a gate of the operating transistor being connected with one end of the storage capacitor and the pixel select transistor, one of a source and a drain of the operating transistor being connected with the one voltage supply line, the other of the source and the drain of the operating transistor being in an open state, and one of a plurality of common lines being connected with the other end of the storage capacitor, the inspection device comprising:

an inspection potential generating circuit which generates inspection potentials supplied to the scanning lines, the voltage supply lines, and the common lines;

a charge-sense circuit connected with the signal lines;

a timing signal generating circuit which generates a timing signal for driving the scanning lines, the signal lines, the voltage supply lines, and the common lines; and

a determining circuit which determines whether or not a defect exists in each of the plurality of pixels based on an output from the charge-sense circuit,

wherein the inspection potential generating circuit and the charge-sense circuit supply potentials to charge the storage capacitor in a charging period, supply potentials to discharge the storage capacitor in a sensing period, supply potentials to cancel an influence of a parasitic capacitor between the gate of the operating transistor and the one voltage supply line in the charging period and a sensing period, and measure discharge current from the storage capacitor by using the charge-sense circuit in the sensing period.

24. The inspection device as defined in claim 23,

wherein a vertical driver circuit which selectively drives the scanning lines and a horizontal driver circuit which selectively drives the signal lines are provided on the active matrix substrate, and

wherein the timing signal generating circuit supplies a timing signal to the vertical driver circuit and the horizontal driver circuit to make a charge operation and a sense operation to be performed based on functions of the vertical driver circuit and the horizontal driver circuit.

25. A program for inspecting an active matrix substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of voltage supply lines, and a plurality of pixels, each of the plurality of pixels being connected with one of the signal lines, one of the scanning lines, and one of the voltage supply lines, each of the plurality of pixels including a pixel select transistor connected with the one signal line and the one scanning line and an operating transistor, a gate of the operating transistor being connected with the pixel select transistor, one of a source and a drain of the operating transistor being connected with the one voltage supply line, and the other of the source and the drain of the operating transistor being in an open state, the program for causing a computer to perform the procedures comprising:

a first procedure of charging a parasitic capacitor between the gate of the operating transistor and the one voltage supply line;

a second procedure of measuring discharge current from the parasitic capacitor by discharging the parasitic capacitor; and

a third procedure of determining whether or not a defect exists in each of the plurality of pixels based on a value of the discharge current.

26. A computer-readable information storage medium storing the program as defined in claim 25 is recorded.

27. A program for an active matrix substrate for inspecting an active matrix substrate including a plurality of signal lines, a plurality of scanning lines, a plurality of voltage supply lines, and a plurality of pixels, each of the plurality of pixels being connected with one of the signal lines, one of the scanning lines, and one of the voltage supply lines, each of the plurality of pixels including a pixel select transistor connected with the one signal line and the one scanning line, an operating transistor, and a storage capacitor, a gate of the operating transistor being connected with one end of the storage capacitor and the pixel select transistor, one of a source and a drain of the operating transistor being connected with the one voltage supply line, the other of the source and the drain of the operating transistor being in an open state, and one of a plurality of common lines being connected with the other end of the storage capacitor, the program for causing a computer to perform the procedures comprising:

a first procedure of charging the storage capacitor;

a second procedure of measuring discharge current from the storage capacitor by discharging the storage capacitor; and

a third procedure of determining whether or not a defect exists in each of the plurality of pixels based on a value of the discharge current,

wherein the program also causes the computer to cancel an influence of a parasitic capacitor between the gate of the operating transistor and the one voltage supply line in the first procedure and the second procedure.

28. A computer-readable information storage medium storing the program as defined in claim 27 is recorded.