Transimpedance amplifier

• US 6,816,010 B2
• Filed: 12/20/2002
• Issued: 11/09/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Petersen, Anders K., Huang, Lawrence L., Seetharaman, Shivakumar, Asmanis, Georgios S.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US10/325,048
• Publication Number:
  US 20040119542A1
• Time in Patent Office: 690 Days
• Field of Search: 330/85, 330/277, 330/308, 330/291, 330/110, 375/318, 250/214.R, 398/202
• US Class Current: 330/85
• CPC Class Codes: H03F 3/082 with FET's H03F3/085 takes precedence

Abstract

Disclosed is a transimpedance amplifier comprising a multistage amplifier and a feedback circuit coupled between a single ended input terminal and one of a plurality of differential output terminals of the multistage amplifier. The feedback circuit may control an input voltage at the single input terminal to substantially maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

Claims

1. A transimpendance amplifier comprising:

a multistage amplifier comprising differential output terminals to provide an output signal in response to an input signal and an input stage transistor having a gate terminal to receive the input signal from a photodiode; and

a feedback transistor comprising a gate terminal coupled to one of the differential output terminals, and one of a source terminal and a drain terminal coupled to the gate terminal of the input stage transistor, wherein the feedback transistor is selected to maintain an input voltage at the gate terminal of the input stage transistor to maintain a set or predetermined transconductance between the gate terminal of the input stage transistor and the differential output terminals.

2. The transimpedance amplifier of claim 1, wherein the multistage amplifier comprises an input impedance substantially matching an impedance of the photodiode.

3. A transimpendance amplifier comprising:

a multistage amplifier comprising differential output terminals and a single ended input terminal to receive an input signal from a photodiode;

a transistor comprising a gate terminal coupled to one of the differential output terminals, and one of a source terminal and a drain terminal coupled to the single ended input terminal; and

resistor coupled between the single ended input terminal and the one of a source terminal and drain terminal of the, and wherein the resistor comprises a resistance selected to maintain an input voltage at the single ended input to maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

4. A transimpendance amplifier comprising:

a multistage amplifier comprising differential output terminals to provide an output signal in response to an input signal and an input stage transistor having a gate terminal to receive the input signal from a photodiode; and

a feedback circuit coupled between the gate terminal of the input stage transistor and a differential output terminal to maintain an input voltage at the gate terminal of the input transistor to substantially maintain a set or predetermined transconductance between the gate terminal of the input stage transistor and the differential output terminals.

5. The transimpedance amplifier of claim 4, wherein the input transistor comprises a capacitive input impedance that is substantially proportional to an input width of the input transistor.

6. The transimpedance amplifier of claim 5, wherein the input transistor comprises a transconductance that is substantially proportional to the input width.

7. The transimpedance amplifier of claim 4, wherein the feedback circuit comprises a source follower circuit.

8. The transimpedance amplifier of claim 5, wherein the transimpedance amplifier is formed in a complementary metal oxide semiconductor device.

9. A system comprising:

a photodiode;

a transimpedance amplifier coupled to the photodiode to provide a differential output signal;

a data recovery circuit to provide a serial data signal in response to the differential output signal;

a deserializer to provide a parallel data signal in response to the serial data signal, wherein the transimpedance amplifier comprises;

a multistage amplifier comprising differential output terminals to provide the differential output signal in response to an input signal and an input stage transistor having a gate terminal to receive the input signal from the photodiode; and

a feedback transistor comprising a gate terminal coupled to one of the differential output terminals, and one of a source terminal and a drain terminal coupled to the gate terminal of the input stage transistor, wherein the feedback transistor is selected to maintain an input voltage at the gate terminal of the input stage transistor to maintain a set or predetermined transconductance between the gate terminal of the input stage transistor and the differential output terminals.

10. The system of claim 9, the system further comprising a SONET framer to receive the parallel data signal.

11. The system of claim 10, wherein the system further comprises a switch fabric coupled to the SONET framer.

12. The system of claim 9, the system further comprising an Ethernet MAC to receive the parallel data signal at a media independent interface.

13. The system of claim 12, wherein the system further comprises a multiplexed data bus coupled to the Ethernet MAC.

14. The system of claim 12, wherein the system further comprises a switch fabric coupled to the Ethernet MAC.

15. The system of claim 9, wherein the multistage amplifier comprises an input impedance substantially matching an impedance of the photodiode.

16. A system comprising:

a photodiode;

a transimpedance amplifier coupled to the photodiode to provide a differential output signal;

a data recovery circuit to provide a serial data signal in response to the differential output signal;

a deserializer to provide a parallel data signal in response to the serial data signal, wherein the transimpedance amplifier comprises;

a multistage amplifier comprising a single ended input terminal to receive an input signal from the photodiode and differential output terminals to provide the differential output signal;

a transistor comprising a gate terminal coupled to one of the differential output terminals, and one of a source terminal and a drain terminal coupled to the single ended input terminal; and

a resistor coupled between the single ended input terminal and the one of a source terminal and drain terminal of the transistor, and wherein the resistor comprises a resistance selected to maintain an input voltage at the single ended input to maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

32. The system of claim 16, the system further comprising a SONET framer to receive the parallel data signal.

33. The system of claim 32, wherein the system further comprises a switch fabric coupled to the SONET framer.

34. The system of claim 16, the system further comprising an Ethernet MAC to receive the parallel data signal at a media independent interface.

35. The system of claim 34, wherein the system further comprises a multiplexed data bus coupled to the Ethernet MAC.

36. The system of claim 34, wherein the system further comprises a switch fabric coupled to the Ethernet MAC.

37. The system of claim 16, wherein the multistage amplifier comprises an input impedance substantially matching an impedance of the photodiode.

17. A system comprising:

a photodiode;

a transimpedance amplifier coupled to the photodiode to provide a differential output signal;

a data recovery circuit to provide a serial data signal in response to the differential output signal; and

a deserializer to provide a parallel data signal in response to the serial data signal, wherein the transimpedance amplifier comprises;

a multistage amplifier comprising differential output terminals to provide an output signal in response to an input signal and an input stage transistor having a gate terminal to receive the input signal from the photodiode; and

a feedback circuit coupled between the gate terminal of the input stage transistor and a differential output terminal to maintain an input voltage at the gate terminal of the input stage transistor to substantially maintain a set or predetermined transconductance between the gate terminal of the input stage transistor and the differential output terminals.

18. The system of claim 17, the system further comprising a SONET framer to provide the parallel data signal.

19. The system of claim 18, wherein the system further comprises a switch fabric coupled to the SONET framer.

20. The system of claim 17, the system further comprising an Ethernet MAC to provide the parallel data signal at a media independent interface.

21. The system of claim 20, wherein the system further comprises a multiplexed data bus coupled to the Ethernet MAC.

22. The system of claim 20, wherein the system further comprises a switch fabric coupled to the Ethernet MAC.

23. The system of claim 17, wherein the input impedance comprises a capacitive impedance that is substantially proportional to an input width of an input transistor of the multistage amplifier.

24. The system of claim 23, wherein the input transistor comprises a transconductance that is substantially proportional to the input width.

25. The system of claim 17, wherein the feedback circuit comprises a source follower circuit.

26. A method comprising:

receiving an input signal from a photodiode at a gate terminal of an input stage transistor of a multistage amplifier;

providing a voltage of a pair of differential output terminals of the multistage amplifier to a gate terminal of a feedback transistor; and

providing to the gate terminal of the input stage transistor a current from one of a source terminal and a drain terminal of the feedback transistor, wherein the feedback transistor is selected to maintain an input voltage at the gate terminal of the input stage transistor to maintain a set or predetermined transconductance between the gate terminal of the input stage transistor and the differential output terminals.

27. The method of claim 26, wherein the multistage amplifier comprises an input impedance substantially matching an impedance of the photodiode.

28. A method comprising:

receiving an input signal from a photodiode at a single ended input terminal of a multistage amplifier;

providing a voltage of a pair of differential output terminals of the multistage amplifier to a gate terminal of a transistor;

providing to the single ended input terminal a current from one of a source terminal and a drain terminal of the transistor; and

coupling a resistance between the transistor and the single ended input terminal to maintain an input voltage at the single ended input to maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

29. A method comprising:

receiving an input signal from a photodiode at a gate terminal of an input stage transistor of a multistage amplifier; and

maintaining an input voltage at the single ended input terminal to substantially maintain a set or predetermined transconductance between the gate terminal of the input stage amplifier and the differential output terminals in response to a voltage at one of the differential output terminals.

30. The method of claim 29, wherein the input stage transistor comprises a capacitive input impedance that is substantially proportional to an input width of the input stage transistor of the multistage amplifier, and wherein the method further comprises substantially matching the capacitive input impedance with an impedance of the photodiode.

31. The method of claim 30, wherein the input stage transistor comprises a transconductance that is substantially proportional to the input width.