High-speed analog-to-digital converter using a unique gray code
First Claim
1. An analog to digital converter comprising:
- a plurality of comparators for receiving a multilevel signal generated according to a code for which the maximum number of bit-toggles incurred in a bit channel while sequentially traversing the code is minimized;
a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs, whereby the analog to digital converter has a design that reduces dissipated power and increases achievable operational speeds for communications.
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Abstract
A method for high speed communications uses an inventive Q-Gray code. The Q-Gray code simplifies the hardware needed to convert analog Q-Gray code signals to digital signals. An analog-to-digital converter can use a plurality of comparators for receiving the multilevel signal and a plurality of decoder blocks coupled to comparators for decoding the multilevel signal. Each decoder block can include an equal number of inputs. Specifically, each decoder block can also include a parity detector with an equal number of inputs. Each decoder block can also employ a bank of identical parity detectors relative to another decoder block. Each comparator of the analog to digital converter can have an individually or externally adjustable (or both) threshold level.
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Citations
47 Claims
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1. An analog to digital converter comprising:
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a plurality of comparators for receiving a multilevel signal generated according to a code for which the maximum number of bit-toggles incurred in a bit channel while sequentially traversing the code is minimized;
a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs, whereby the analog to digital converter has a design that reduces dissipated power and increases achievable operational speeds for communications. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An analog to digital converter comprising:
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a plurality of comparators with adjustable thresholds for receiving a multilevel signal;
a plurality of decoder blocks coupled to the comparators for decoding the multilevel signal, wherein each decoder block comprises a plurality of identical parity detectors relative to another decoder block, whereby the analog to digital converter has a design that reduces dissipated power and increases communication speed. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An analog to digital converter comprising:
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a plurality of comparators for receiving a multilevel signal generated by a code for which the bit error rate is substantially evenly distributed across each bit channel when decoded;
a plurality of decoder blocks coupled to the comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of parity detectors, whereby the analog to digital converter reduces power consumption. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. An analog to digital converter comprising:
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a plurality of comparators for receiving a multilevel signal, each comparator having an individually adjustable threshold level;
a plurality of decoder blocks coupled to the comparators for decoding the multilevel signal, wherein each decoder block comprises identical hardware relative to another decoder block, whereby the analog to digital converter has a design that increases communication speeds. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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30. An analog to digital converter comprising:
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a plurality of comparators for receiving a multilevel signal generated according to a three bit Gray code derived from a bit translation operating list comprising ABCBABC with an operator comprising B and the operator returning an original seed from a last word in the three bit Gray code;
a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs. - View Dependent Claims (31, 32)
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33. An analog to digital converter comprising:
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a plurality of comparators for receiving a multilevel signal generated according to a four bit Gray code derived from a bit translation operating list comprising CBCADABCBADBDCD with an operator comprising A and the operator returning an original seed from a last word in the four bit Gray code;
a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs. - View Dependent Claims (34, 35)
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36. An analog to digital converter comprising:
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a plurality of comparators for receiving a multilevel signal generated according to a five bit Gray code derived from a bit translation operating list comprising ABACABADABEBDCDEBEDCACDECEBDCDE, with an operator comprising D and the operator returning an original seed from a last word in the five bit Gray code;
a plurality of decoder blocks coupled to comparators for decoding the multilevel signal, wherein each decoder block comprises an equal number of inputs. - View Dependent Claims (37, 38)
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39. A method for high speed communications comprising:
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receiving data;
modulating the data to produce a multilevel signal according to a three bit Gray code derived from a bit translation operating list comprising ABCBABC with an operator comprising B and the operator returning an original seed from a last word in the three bit Gray code;
receiving the multilevel signal; and
converting the multilevel signal to a set of binary signals with decoder blocks, wherein each decoder block comprises an equal number of inputs. - View Dependent Claims (40, 41)
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42. A method for high speed communications comprising:
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receiving data;
modulating the data to produce a multilevel signal according to a four bit Gray code derived from a bit translation operating list comprising CBCADABCBADBDCD with an operator comprising A and the operator returning an original seed from a last word in the four bit Gray code;
receiving the multilevel signal; and
converting the multilevel analog signal to a set of binary signals with decoder blocks, wherein each decoder block comprises an equal number of inputs. - View Dependent Claims (43, 44)
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45. A method for high speed communications comprising:
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receiving data;
modulating the data to produce a multilevel signal to produce a five bit Gray code derived from a bit translation operating list comprising ABACABADABEBDCDEBEDCACDECEBDCDE, with an operator comprising D and the operator returning an original seed from a last word in the five bit Gray code;
receiving the multilevel signal; and
converting the multilevel signal to a set of binary signals with decoder blocks, wherein each decoder block comprises an equal number of inputs. - View Dependent Claims (46, 47)
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Specification