Semiconductor memory device having multi-bit testing function

• US 6,816,422 B2
• Filed: 11/12/2002
• Issued: 11/09/2004
• Est. Priority Date: 05/13/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hamade, Kei, Furutani, Kiyohiro, Kono, Takashi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/291,776
• Publication Number:
  US 20030210594A1
• Time in Patent Office: 728 Days
• Field of Search: 365/201, 365/189.07, 365/189.08, 365/233
• US Class Current: 365/201
• CPC Class Codes: G11C 2029/0405 comprising complete test loop
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.

Claims

1. A semiconductor memory device comprising:

a memory cell array for storing data;

a determination circuit for receiving expected value data for logic levels of read data of a plurality of bits read in parallel from said memory cell array, and determining whether the logic levels of said read data coincide with a logic level of said expected value data in a multi-bit test;

an output circuit for outputting a determination result of said determination circuit;

an input circuit for receiving degenerated data obtained by degenerating write data of a plurality of bits written in parallel to said memory cell array;

a test mode control circuit for generating a write data pattern signal for said write data of the plurality of bits on the basis of an internal test pattern setting signal generated internally;

a write data inversion circuit for inverting logic level of a part of said write data of the plurality of bits written in parallel to said memory cell array on the basis of said write data pattern signal in said multi-bit test; and

a read data inversion circuit for re-inverting the logic level of the data the logic level of which is inverted by said write data inversion circuit for said read data of the plurality of bits read in parallel from said memory cell array, and outputting the re-inverted read data of the plurality of bits to said determination circuit.

2. The semiconductor memory device according to claim 1, wherein

said determination circuit determines whether a logic level of degenerated data obtained by degenerating said read data of the plurality of bits coincides with the logic level of said expected value data.

3. The semiconductor memory device according to claim 2, further comprising:

a degeneration circuit for degenerating said read data of the plurality of bits, and outputting said degenerated data; and

a read amplifier for amplifying a signal level of received data, and outputting the data to said output circuit, wherein

said read amplifier amplifies the signal level of read data read from said memory cell array and outputs the read data to said output circuit when the semiconductor memory device operates normally, and

said read amplifier receives said degenerated data outputted from said degeneration circuit and outputs the determination result of said determination circuit to said output circuit in said multi-bit test.

4. The semiconductor memory device according to claim 3, wherein

said degeneration circuit outputs said degenerated data indicating a first degeneration result when all of the logic levels of said read data of the plurality of bits read in parallel from said memory cell array are a first logic level, outputs said degenerated data indicating a second degeneration result when all of the logic levels of said read data of the plurality of bits read in parallel from said memory cell array are a second logic level, and outputs said degenerated data indicating a third degeneration result when all of the logic levels of said read data of the plurality of bits read in parallel from said memory cell array do not coincide each other, and

said determination circuit determines that writing/reading of data of said plurality of bits have been normally performed when said degenerated data indicates said first degeneration result and the logic level of said expected value data is said first logic level or when said degenerated data indicates said second degeneration result and the logic level of said expected value data is said second logic level.

5. The semiconductor memory device according to claim 1, wherein

said expected value data is set from an outside of the semiconductor memory device through one of terminals employed when the semiconductor memory device normally operates.

6. The semiconductor memory device according to claim 1, wherein

said internal test pattern setting signal is generated internally on the basis of one of a plurality of commands issued to the semiconductor memory device.

7. The semiconductor memory device according to claim 1, wherein

said test mode control circuit receives an external test pattern setting signal inputted from one predetermined terminal, and generates said write data pattern signal on the basis of said internal test pattern setting signal and said external test pattern setting signal.