System-on-a-chip

• US 6,816,750 B1
• Filed: 06/09/2000
• Issued: 11/09/2004
• Est. Priority Date: 06/09/2000
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Klaas, Jeff
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): Rapp, Chad
• Application Number:
  US09/590,506
• Time in Patent Office: 1,614 Days
• Field of Search: 700/121, 710/2, 710/8, 710/22, 710/25, 710/126, 710/128, 710/129, 710/260, 711/102, 711/103, 711/104, 712/32, 712/33, 712/35, 712/37, 712/41, 712/228, 716/17, 345/200-216
• US Class Current: 700/121
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus 102 through a bus bridge 113. A first set of processing resources operate from high speed bus 102 and includes an external memory interface 108, a direct memory access engine 105 for controlling the exchange of information through memory interface 108, and a boot memory 104 for storing boot code. A second set of processing resources operate from peripheral bus 103 and includes an interrupt controller 115 for issuing interrupt requests to microprocessor 101, a set of programmable timers 117 for generating timed interrupt signals, and a phase locked loop 131 for generating timing signals.

Claims

1. A system fabricated on a single integrated circuit chip comprising:

a microprocessor operating from a high speed bus and providing overall control of said system;

a peripheral bus operating in conjunction with said high speed bus through a bus bridge; and

a first set of processing resources operating from said high speed bus and a second set of processing resources operating from said peripheral bus, said first set of processing resources comprising;

a memory interface for interfacing said system with an external memory;

a direct memory access engine for controlling the exchange of information between selected ones of said resources and said external memory through said memory interface; and

a boot memory for storing boot code for initiating operation of said system;

and said second set of processing resources comprising;

an interrupt controller for issuing interrupt requests to said microprocessor in response to interrupt signals from selected ones of said resources;

a set of programmable timers for generating timed interrupt signals; and

a phase-locked loop for generating timing signals for timing selected operations of said system.

2. The system of claim 1 wherein said microprocessor communicates with said high speed bus via a tri-state buffering interface.

3. The system of claim 1 wherein said high speed bus comprises an Advanced Microprocessor Bus Architecture bus.

4. The system of claim 1 wherein said peripheral bus comprises an Advanced Peripheral Bus.

5. The system of claim 1 wherein a selected one of said first set of resources communicates with said high speed bus via a tri-state interface.

6. The system of claim 1 wherein a selected one of said second set of resources communicates with said peripheral bus via a tri-state interface.

7. The memory of claim 1 wherein said direct memory access engine comprises a plurality of processing paths associated with a plurality of channels, a priority assigned to each channel rotating in accordance with a selected scheme.

8. The memory of claim 1 wherein said direct memory access engine comprises a plurality of processing paths associated with a plurality of channels, selected ones of said processing path associated with CRC circuitry.

9. The system of claim 1 wherein said first set of processing resources further comprises:

circuitry for driving a display device;

a JTAG test interface; and

a communications port.

10. The system of claim 1 wherein said second set of processing resources further includes:

an interface for communicating with an external manual input device; and

an interface for exchanging data with an external digital device.

11. A system-on-a-chip based on a reduced instruction set processor core operating in conjunction with a microprocessor bus and a peripheral bus operating from the microprocessor bus through a bridge comprising:

a first set of processing resources operating from the microprocessor bus, at least one of the first set of processing resources communicating with the microprocessor bus through a tri-state buffer interface, comprising;

a memory controller for communicating with an external memory;

a direct memory access engine for controlling the communications between requesting subsystems forming a part of said system and said external memory;

circuitry for driving an external display; and

first port for communicating with an external digital device; and

a second set of processing resources operating from the peripheral bus, at least one of the second set of processing resources communicating with the peripheral bus through a tri-state buffer interface, comprising;

an interrupt controller for generating interrupt requests to the microprocessor in response to interrupt signals from selected system resources;

an interface for communicating with an external manual input device;

second port for communicating with an external digital device; and

a set of timers for selectively generating interrupt signals.

12. The system-on-a-chip of claim 11 wherein said memory controller comprises a static random access memory controller.

13. The system-on-a-chip of claim 11 wherein said memory controller comprises a dynamic random access memory controller.

14. The system-on-a-chip of claim 11 wherein said circuitry for driving an external display comprises an LCD interface.

15. The system-on-a-chip of claim 11 wherein said circuitry for driving an external display comprises a graphics engine.

16. The system-on-a-chip of claim 11 wherein said first port comprises an Ethernet port.

17. The system-on-a-chip of claim 11 wherein said first port comprises a universal serial bus port.

18. The system-on-a-chip of claim 11 wherein said interface for communicating with an external manual input device is operable to interface with a touchscreen device.

19. The system-on-a-chip of claim 11 wherein said interface for communicating with an external manual input device is operable to interface with a key matrix.

20. The system-on-a-chip of claim 11 wherein said second port comprises a universal asynchronous receive-transmit interface.

21. The system-on-a-chip of claim 11 wherein said second port comprises an SPI interface.

22. The system-on-a-chip of claim 11 wherein said set of timers comprises:

a watchdog timer; and

a programmable interval timer.

23. An integrated circuit comprising:

a reduced instruction set computing microprocessor operating from an Advanced Microprocessor Bus Architecture high-speed bus;

direct memory access circuitry operating from said high-speed bus for managing the transfer of data between selected circuits disposed on said integrated chip and memory;

boot memory operating from said high-speed bus for booting said integrated circuit;

an Ethernet port operating from said high-speed bus for interfacing with an external network;

an Advanced Peripheral Bus operating from said high speed bus through a bus bridge;

a Universal Asynchronous Receive-Transmit interface operating from said peripheral bus for interfacing with an external digital device;

a touchscreen interface operating from said peripheral bus for interfacing with an external touchscreen device; and

a watchdog timer operating from said peripheral bus for monitoring operation of said integrated circuit a graphic engine operating from said high speed bus.

24. The integrated circuit of claim 23 and further comprising circuitry for driving an LCD display operating from said high-speed bus.

25. The integrated circuit of claim 23 wherein said microprocessor comprises separate instruction and data caches.

26. The integrated circuit of claim 23 wherein said microprocessor comprises and Advanced RISC Machine processor core.

27. The integrated circuit of claim 23 and further comprising a serial port operating from said high-speed bus.

28. The integrated circuit of claim 23 and further comprising a serial port operating from said peripheral bus.

29. The integrated circuit of claim 23 and further comprising a programmable phase-locked loop operating from said peripheral bus.

30. The integrated circuit of claim 23 wherein a selected one of said Ethernet port and said direct memory access circuitry is selectively coupled to said high speed bus through a tri-state buffer.

31. The integrated circuit of claim 23 wherein a selected one of said Universal Asynchronous Receive-Transmit interface, said touchscreen interface and said watchdog timer, is selectively coupled to said peripheral bus through a tri-state buffer.