Bus precharge during a phase of a clock signal to eliminate idle clock cycle

• US 6,816,932 B2
• Filed: 05/15/2001
• Issued: 11/09/2004
• Est. Priority Date: 10/06/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rowlands, Joseph B., Cho, James Y., Pearce, Mark H.
• Primary Examiner(s): Park, Ilwoo
• Application Number:
  US09/858,778
• Publication Number:
  US 20020041633A1
• Time in Patent Office: 1,274 Days
• Field of Search: 710/100, 710/300, 710/305, 326/31, 326/33, 326/34, 326/86, 326/87, 326/90, 326/91, 365/203, 365/185.01, 365/185.18, 365/185.25, 365/233
• US Class Current: 710/100
• CPC Class Codes: G06F 13/4077 Precharging or discharging
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Claims

1. An apparatus comprising:

a bus, including at least one line, to couple a plurality of devices to transfer a value on the bus between the devices by having the devices arbitrate for the bus; and

a circuit coupled to the bus to receive a clock signal for the bus, the clock signal having a rising edge and a falling edge during use, wherein the circuit is configured to precharge the at least one line during at least a portion of a first interval of the clock signal, the first interval being between an occurrence of a first edge, the first edge being one of the rising edge or the falling edge, and an occurrence of a second edge, the second edge being the other one of the rising edge or the falling edge, and wherein the bus is driven to transfer the value during a second interval of the clock signal, and in which the circuit having precharge points along the at least one line to perform rapid precharge of the plurality of devices distributed along the bus.

2. The apparatus as recited in claim 1 wherein the first edge is the rising edge and the second edge is the falling edge.

3. The apparatus as recited in claim 1 wherein the first edge is the falling edge and the second edge is the rising edge.

4. The apparatus as recited in claim 1 wherein the circuit comprises transistors distributed along the length of the at least one line at the precharge points and wherein the transistors are to be activated to precharge the at least one line.

5. The apparatus as recited in claim 4 wherein a gate terminal of each of the transistors is coupled to receive the clock signal.

6. The apparatus as recited in claim 4 wherein a gate terminal of each of the transistors is coupled to receive a signal generated by a second circuit responsive to the clock signal.

7. The apparatus as recited in claim 4 wherein the transistors are PMOS transistors.

8. The apparatus as recited in claim 1 wherein the circuit precharges the at least one line to a high voltage.

9. The apparatus as recited in claim 1 wherein the circuit precharges the at least one line to a low voltage.

10. The apparatus as recited in claim 1 wherein the at least one line is one of a differential pair of lines corresponding to a signal on the bus.

11. The apparatus as recited in claim 1 wherein the bus comprises an address bus and a data bus.

12. The apparatus as recited in claim 11 wherein the bus further comprises response lines carrying signals for maintaining coherency in response to transactions on the bus.

13. The apparatus as recited in claim 11 wherein the bus further comprises arbitration lines.

14. The apparatus as recited in claim 1 wherein the clock signal defines a clock cycle, and wherein the second interval occurs earlier in the clock cycle than the first interval.

15. A method comprising:

precharging at least one line of a bus used to couple a plurality of devices to transfer a value on the bus between the devices in which the devices arbitrate for the bus, wherein the precharging to occur during at least a portion of a first interval a clock signal for the bus, the clock signal having a rising edge and a falling edge during use, the first interval being between an occurrence of a first edge, the first edge being one of the rising edge or the falling edge, and an occurrence of a second edge, the second edge being the other of the rising edge or the falling edge, and wherein the precharging to occur at a plurality of precharging points distributed along the at least one line to perform rapid precharging of the plurality of devices distributed along the bus; and

transferring the value on the bus during a second interval of the clock signal, when a particular device wins arbitration of the bus.

16. The method as recited in claim 15 wherein the first edge is the rising edge and the second edge is the falling edge.

17. The method as recited in claim 15 wherein the first edge is the falling edge and the second edge is the rising edge.

18. The method as recited in claim 15 wherein the precharging comprises precharging the at least one line to a high voltage.

19. The method as recited in claim 15 wherein the precharging comprises precharging the at least one line to a low voltage.

20. The method as recited in claim 15 wherein the at least one line is one of a differential pair of lines corresponding to a signal on the bus.

21. The method as recited in claim 15 wherein the clock signal defines a clock cycle, and wherein the second interval occurs earlier in the clock cycle than the first interval.