Integrated circuit inductors

• US 6,817,087 B2
• Filed: 03/18/2002
• Issued: 11/16/2004
• Est. Priority Date: 07/09/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/100,706
• Publication Number:
  US 20020095769A1
• Time in Patent Office: 974 Days
• Field of Search: 296/04, 296/05, 296/06, 336/173, 336/186, 336/83, 336/84, 336/98, 336/147
• US Class Current: 29/604
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 37/00 Fixed inductances not covered by group H01F17/00
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49037 Using reference point/surface to facilitate measuring
• CPC Class Codes: Y10T 29/49069 Data storage inductor or core
• CPC Class Codes: Y10T 29/49071 by winding or coiling
• CPC Class Codes: Y10T 29/49073 by assembling coil and core
• CPC Class Codes: Y10T 29/49075 including permanent magnet or core

Abstract

The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloys, and oxides. The inductor is compatible with integrated circuit manufacturing techniques and eliminates the need in many systems and circuits for large off chip inductors. A sense and measurement coil, which is fabricated on the same substrate as the inductor, provides the capability to measure the magnetic field or flux produced by the inductor. This on chip measurement capability supplies information that permits circuit engineers to design and fabricate on chip inductors to very tight tolerances.

Claims

1. An integrated circuit comprising:

a coated substrate having a circuit formed on the coated substrate and having a plurality of substantially parallel perforations; and

a coil routed through the plurality of substantially parallel perforations, and the coil operably coupled to the circuit.

2. The integrated circuit of claim 1, wherein the coating is a magnetic material.

3. The integrated circuit of claim 2, wherein the magnetic material comprises nickel and iron.

4. An integrated circuit comprising:

a substrate having a coating and a plurality of parallel perforations that connect two sides of the substrate;

a circuit formed on the substrate;

first coil segments routed through the plurality of substantially parallel perforations;

second coil segments connecting the first coils segments to form a coil; and

wherein the coil is operably coupled to the circuit.

5. The integrated circuit of claim 4, wherein the first coil segments comprise a first conductor and the second coil segments comprise a second conductor.

6. The integrated circuit of claim 4, wherein the coating comprises a magnetic film.

7. The integrated circuit of claim 6, wherein magnetic film is covered with an insulating layer.

8. The integrated circuit of claim 4, wherein the coil has a rectangular cross-section.

9. The integrated circuit of claim 4, wherein the circuit includes memory cells.

10. An integrated circuit comprising:

a substrate having a plurality of parallel through-perforations;

a conductive path passing through the through perforations and around first and second sides of the substrate;

a circuit formed on the substrate and connected to the conductive path.

11. The integrated circuit of claim 10, wherein the conductive path comprises one of gold, copper and aluminum.

12. The integrated circuit of claim 10, wherein the conductive path partially surrounds at least one coating formed on at least one of the first and second sides.

13. The integrated circuit of claim 12, wherein the at least one coating includes a magnetic film.

14. The integrated circuit of claim 13, wherein the at least one coating includes an insulator layer.

15. An integrated circuit comprising:

a substrate having first and second regions;

a magnetic film covering a portion of the first region of the substrate;

a plurality of parallel perforations formed in the first region of the substrate;

a coil formed in the first region by routing one or more conductors through the parallel perforations and around first and second sides of the substrate; and

a circuit formed in the second region and electrically connected to the coil.

16. The integrated circuit of claim 15, wherein the magnetic film comprises iron and nickel.

17. The integrated circuit of claim 15, wherein the coating includes an insulating layer covering the magnetic film.

18. The integrated circuit of claim 17, wherein the insulating layer comprises polyimide.

19. The integrated circuit of claim 17, wherein the insulating layer is a dielectric.

20. The integrated circuit of claim 15, wherein the substrate is a semiconductor material.

21. The integrated circuit of claim 15, wherein the coil comprises two or more conductors having different resistivities.

22. An integrated circuit comprising:

a substrate;

a coating covering a portion of the substrate;

first and second parallel rows of parallel perforations formed in the substrate;

a conductive path formed by passing a conductor through the first and second parallel rows of parallel perforations to form a coil, with a portion of the coil surrounding the coating;

leads connected to the coil; and

a circuit connected to the leads.

23. The integrated circuit of claim 22, wherein the substrate comprises a material selected from the group of materials comprising:

silicon, germanium, gallium arsenide and silicon carbide.

24. The integrated circuit of claim 22, wherein the coating comprises a ferromagnetic material.

25. The integrated circuit of claim 24, wherein the coating includes an insulator covering the ferromagnetic material.

26. The integrated circuit of claim 22, wherein the circuit included memory cells.

27. The integrated circuit of claim 22, further including a sense inductor magnetically coupled to the coil.

28. An integrated circuit comprising:

a semiconductor substrate;

a magnetic film covering a first select region of the substrate;

parallel perforations formed in the substrate so as to partially surrounding the magnetic film;

first conductive segments formed in the parallel perforations so as to connect first and second substrate surfaces;

second conductive segments connected to the first conductive segments to form a coil surrounding a select volume of the semiconductor and surrounding the magnetic film; and

a circuit formed in a second select region of the substrate and connected to the coil.

29. The integrated circuit of claim 28, further including an insulating layer covering a portion of the coil and the magnetic film.

30. The integrated circuit of claim 28, wherein the first and second conductive segments comprise at least one of gold, aluminum and copper.

31. An integrated circuit comprising:

a substrate;

a coating covering a portion of the substrate;

first and second rows of parallel perforations connected opposite sides of the substrate and surrounding first and second sides of the coating;

a coil routed through the parallel perforations so as to enclose a volume portion of the substrate and the coating; and

a circuit operatively connected to the coil.

32. The integrated circuit of claim 31, wherein the coating includes an insulating layer covering a portion of the coil.

33. The integrated circuit of claim 31, wherein the coil comprises at least one of gold, aluminum and copper.

34. The integrated circuit of claim 31, wherein the coil has an inductance and the coating is designed to increase the coil inductance.

35. The integrated circuit of claim 31, further including a sense inductor formed on the substrate and magnetically coupled to the coil.

36. The integrated circuit of claim 31, further including a sense inductor formed at least partially within in the substrate and magnetically coupled to coil.