Method of fabricating complementary high-voltage field-effect transistors

• US 6,818,490 B2
• Filed: 08/26/2003
• Issued: 11/16/2004
• Est. Priority Date: 01/24/2001
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US10/647,925
• Publication Number:
  US 20040036115A1
• Time in Patent Office: 448 Days
• Field of Search: 257/343, 257/369, 257/409, 438/199, 438/301, 438/197, 438/558, 438/526, 438/370, 438/282, 438/188
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of fabricating complementary high-voltage field-effect transistors in a substrate of a first conductivity type includes forming first and second well regions of a second conductivity type in the substrate. A first drain region of the second conductivity type is formed in the first well region, and a first source region is formed in the substrate adjacent the first well region. Second and third drain regions of the first conductivity type are formed in the second well region separated from one another. A second source region of the first conductivity type Is formed In the second well region separated from the second drain region. First and second buried layers are formed within the first and second well regions, respectively, with the second buried layer connected to the second and third drain regions.

Claims

1. A method of fabricating complementary power transistors in a substrate of a first conductivity type comprising:

forming first and second well regions of a second conductivity type opposite to the first conductivity type in the substrate;

forming first and second drain regions of the first conductivity type in the first well region, the second drain region being separated from the first drain region;

forming a third drain region of the second conductivity type in the second well region;

forming first and second buried layers within the first and second well regions, respectively, the first buried layer adjoining the first and second drain regions; and

forming first and second insulated gates.

2. The method according to claim 1 wherein the first conductivity type is P-type.

3. The method according to claim 1 wherein the first and second buried layers are formed simultaneously by implanting a first dopant.

4. The method according to claim 3 wherein the dopant is boron.

5. A method of fabricating complementary high-voltage field-effect transistors (HVFETs) in a substrate of a first conductivity type comprising:

forming first and second well regions of a second conductivity type in the substrate;

forming a first source region In the substrate adjacent the first well region;

forming a first drain region of the second conductivity type in the first well region;

forming second and third drain regions of the first conductivity type in the second well region, the second drain region being separated from the third drain region;

forming a second source region of the first conductivity type in the second well region, the second source region being separated from the second drain region;

forming first and second buried layers within the first and second well regions, respectively, the second buried layer being connected to the second and third drain regions; and

forming first and second Insulated gates.

6. The method of claim 5 wherein the first insulated gate is formed above an area of the substrate that separates the first source region from the first well region.

7. The method of claim 6 wherein the second insulated gate is formed above an area of the second well region that separates the second source region from the second drain region.

8. The method of claim 5 wherein the first conductivity type is P-type and the second conductivity type is N-type.