Method of forming a field effect transistor having a lateral depletion structure

• US 6,818,513 B2
• Filed: 12/18/2003
• Issued: 11/16/2004
• Est. Priority Date: 01/30/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce D.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Dao H.
• Application Number:
  US10/741,464
• Publication Number:
  US 20040132252A1
• Time in Patent Office: 334 Days
• Field of Search: 257/329, 257/330, 257/390, 438/243, 438/268, 438/270, 438/316
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a field effect transistor device includes: forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type, the semiconductor substrate having a major surface and a drain region; forming a source region of the first conductivity type in the well region; forming a trench gate electrode adjacent to the source region; forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and depositing a semiconductor material of the second conductivity type within the stripe trench.

Claims

1. A method of forming a field effect transistor device comprising:

forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type, the semiconductor substrate having a major surface and a drain region;

forming a source region of the first conductivity type in the well region;

forming a trench gate electrode adjacent to the source region;

forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and

depositing a semiconductor material of the second conductivity type within the stripe trench.

2. The method of claim 1 wherein forming a stripe trench occurs after forming a source region.

3. The method of claim 1 wherein the first conductivity type comprises N type and the second conductivity type comprises P type.

4. The method of claim 1 wherein the semiconductor substrate has an orientation and wherein the stripe trench is perpendicular to the orientation of the semiconductor substrate.

5. The method of claim 1 wherein the gate electrode comprises polysilicon.

6. The method of claim 1 wherein the semiconductor material of the second type comprises epitaxial silicon.

7. The method of claim 1 wherein forming the stripe trench occurs after the gate structure, the well region and the source region are formed.

8. The method of claim 1 wherein the method further comprises depositing a dielectric material in the stripe trench.

9. The method of claim 1 wherein the stripe trench extends through the well region.

10. A method of forming a field effect transistor device comprising:

a) forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type having a major surface and a drain region;

b) forming a source region of the first conductivity type formed in the well region;

c) forming a gate electrode adjacent to the source region;

d) forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and

e) depositing a semiconductor material of the second conductivity type within the stripe trench,

wherein at least one of steps a), b), and c) occurs after step e).

11. The method of claim 10 wherein steps d) and e) are performed after steps a), b), and c).

12. The method of claim 10 wherein the gate electrode is a trench gate electrode.

13. The method of claim 10 wherein first conductivity type comprises N type and the second conductivity type comprises P type.

14. The method of claim 10 wherein forming the stripe trench comprises anisotropic etching.

15. A field effect transistor device made according to the process of claim 10.