Methods of depositing two or more layers on a substrate in situ

• US 6,818,517 B1
• Filed: 08/29/2003
• Issued: 11/16/2004
• Est. Priority Date: 08/29/2003
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Maes, Jan Willem
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Lindsay, Jr., Walter L.
• Application Number:
  US10/652,851
• Time in Patent Office: 445 Days
• Field of Search: 438/287, 438/533, 438/585, 438/586, 438/595, 438/690
• US Class Current: 438/287
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

The present invention provides methods of depositing two or more layers on a substrate in situ. In particular, methods are provided for forming a high-k dielectric gate stack on a substrate. Preferably, a high-k dielectric oxide, such as HfO₂, HfSiO₄, ZrO₂ or ZrSiO₄, are deposited on a substrate in a reaction chamber by an atomic layer deposition (ALD) process. A silicon nitride layer is deposited on the substrate by a chemical vapor deposition (CVD) process, preferably a remote plasma enhanced chemical vapor deposition (RPECVD) process. Preferably, the ALD process and the RPECVD process are carried out under substantially isothermal conditions in the same reactor.

Claims

1. A method for forming a high-k gate dielectric stack on a substrate comprising:

loading the substrate into a reaction chamber;

depositing a high-k dielectric layer comprising metal oxide onto the substrate by an atomic layer deposition (ALD) process; and

depositing a silicon nitride layer onto the substrate by a chemical vapor deposition (CVD) process under substantially isothermal conditions with the ALD process,

wherein the substrate is not removed from the reaction chamber between deposition of the high-k dielectric layer and deposition of the silicon nitride layer.

2. The method of claim 1, wherein the silicon nitride layer is deposited over the high-k dielectric layer.

3. The method of claim 1, wherein the high-k dielectric layer is deposited over the silicon nitride layer.

4. The method of claim 1, wherein the substantially isothermal conditions comprise temperatures that differ by less than about 50°

C.

5. The method of claim 1, wherein substantially isothermal conditions comprise deposition at a temperature between about 250°

C. and about 400°

C.

6. The method of claim 5, wherein substantially isothermal conditions comprise deposition at a temperature from about 295°

C. to about 305°

C.

7. The method of claim 1, wherein the metal oxide is selected from the group consisting of oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof.

8. The method of claim 1, wherein the metal oxide is selected from the group consisting of HfO₂, HfSiO₄, ZrO₂ and ZrSiO₄.

9. The method of claim 1, wherein the silicon nitride layer comprises Si₃N₄.

10. The method of claim 1, wherein the silicon nitride layer is deposited by a remote plasma enhanced chemical vapor deposition (RPECVD) process.

11. The method of claim 10, wherein the RPECVD process comprises providing nitrogen radicals and a silane gas to the reaction space.

12. The method of claim 11, wherein the RPECVD process comprises providing nitrogen radicals and a silane gas to the reaction space simultaneously.

13. The method of claim 1, wherein the ALD process comprises providing alternating pulses of a metal source chemical and an oxygen source chemical.

14. The method of claim 13, wherein the metal source chemical is HfCl₄.

15. The method of claim 13, wherein the oxygen source chemical is H₂O.

16. The method of claim 1, wherein the high-k dielectric layer is deposited to a thickness of about 2 nm to about 4 nm.

17. The method of claim 16, wherein the high-k dielectric layer is deposited to a thickness of about 3 nm.

18. The method of claim 1, wherein the silicon nitride layer is deposited to a thickness of about 0.3 nm to about 0.7 nm.

19. The method of claim 18, wherein the silicon nitride layer is deposited to a thickness of about 0.5 nm.

20. The method of claim 1, additionally comprising depositing a layer of polysilicon over the gate dielectric stack.

21. The method of claim 1, additionally comprising forming an interface layer on the substrate prior to forming the high-k dielectric gate stack.

22. The method of claim 21, wherein the interface layer is a silicon oxide or silicon oxynitride layer.

23. A process for forming a gate dielectric stack in an integrated transistor on a semiconductor substrate comprising:

depositing one or more high-k dielectric layers on the semiconductor substrate in a processing chamber by an atomic layer deposition (ALD) process; and

alternating with the deposition of the one or more high-k dielectric oxide layers, depositing one or more silicon nitride layers on the semiconductor substrate in the reaction chamber by a chemical vapor deposition (CVD) process,

wherein the ALD and CVD processes are carried out at substantially isothermal conditions.

24. The method of claim 23, wherein the ALD and CVD processes are carried out within the same processing chamber.

25. The method of claim 23, wherein the substantially isothermal conditions comprise temperatures that differ by less than about 50°

C.

26. The method of claim 23, wherein substantially isothermal conditions comprise deposition at a temperature between about 250°

C. and about 400°

C.

27. The method of claim 26, wherein substantially isothermal conditions comprise deposition at a temperature between about 295°

C. and about 305°

C.

28. A method of depositing two or more layers on a substrate comprising in situ:

depositing a first layer on a substrate in a reaction chamber by an atomic layer deposition (ALD) process; and

depositing a second layer on the substrate in the reaction chamber by a remote plasma enhanced chemical vapor deposition process (RPECVD),

wherein the ALD process and the RPECVD process are conducted under substantially isothermal conditions.

29. The method of claim 28, wherein the ALD process and the RPECVD process are conducted at temperatures that are within about 50°

C. of each other.

30. The method of claim 28, wherein the ALD process and the RPECVD process are conducted at temperatures between about 250°

C. and about 400°

C.

31. The method of claim 30, wherein substantially isothermal conditions comprise deposition at a temperature between about 295°

C. and about 305°

C.

32. The method of claim 28, wherein the first layer comprises a high k metal oxide.

33. The method of claim 28, wherein the second layer comprises silicon nitride.

34. The method of claim 28, wherein the first layer is deposited over the second layer.

35. The method of claim 28, wherein the second layer is deposited over the first layer.