Etching process for high-k gate dielectrics

• US 6,818,553 B1
• Filed: 05/15/2002
• Issued: 11/16/2004
• Est. Priority Date: 05/15/2002
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Yuan-Hung, Yu, Mo-Chiun
• Primary Examiner(s): Thai, Luan
• Assistant Examiner(s): KILDAY, LISA A
• Application Number:
  US10/146,315
• Time in Patent Office: 916 Days
• Field of Search: 438/240, 438/287, 438/591, 438/648, 438/685, 438/689, 438/704, 438/745, 438/761, 438/764, 438/785
• US Class Current: 438/648
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method for forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a pattern gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

Claims

1. A method of forming a gate electrode, comprising the steps of:

providing a substrate having a high-k gate dielectric layer formed thereover;

forming a gate layer over the high-k gate dielectric layer;

forming a gate ARC layer over the gate layer;

patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;

partially etching the high-k gate dielectric layer not under the patterned gate layer and forming a smooth exposed upper surface of the patterned gate layer; and

then removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

2. The method of claim 1, wherein the substrate is a silicon substrate;

the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSiO₄, HfSiO₄, LaSiO₄, YSiO₄, ZrSi_xO_y and HfSi_xO_y;

the gate layer is comprised of a material selected from the group consisting of polysilicon, polycide and a poly-Si/poly-Ge stack structure; and

the gate ARC layer is comprised of a material selected from the group consisting of SiN, SiON, silicon oxide, organic ARC and an organic ARC/SiON stack structure.

3. The method of claim 1, wherein the substrate is a silicon substrate;

the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSi_xO_y and HfSi_xO_y;

the gate layer is comprised of polysilicon; and

the gate ARC layer is comprised of an organic ARC/SiON stack structure.

4. The method of claim 1, wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters:

Ar;

from about 20 to 500 sccm;

power;

from about 200 to 2000 Watts;

temperature;

from about 0 to 100°

C.;

pressure;

from about 5 to 50 mTorr; and

time;

from about 5 to 30 seconds.

5. The method of claim 1, wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters:

Ar;

from about 100 to 200 sccm;

power;

from about 300 to 500 Watts;

temperature;

from about 80 to 90°

C.;

pressure;

from about 20 to 50 mTorr; and

time;

from about 5 to 10 seconds.

6. The method of claim 1, wherein the partially etched high-k gate dielectric layer portions not under the patterned gate layer is etched using an H₂SO₄ wet etch chemistry process conducted at the following parameters:

H₂SO₄;

from about 2 to 20% by volume;

temperature;

from about 25 to 130°

C.; and

time;

from about 10 to 30 seconds.

7. The method of claim 1, wherein the partially etched high-k gate dielectric layer portions not under the patterned gate layer is etched using an H₂SO₄ wet etch chemistry process conducted at the following parameters:

H₂SO₄;

from about 2 to 5% by volume;

temperature;

from about 25 to 50°

C.; and

time;

from about 10 to 20 seconds.

8. The method of claim 1, wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween.

9. The method of claim 1, wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween;

and wherein the Ar sputter or the F-based-chemistry plasma etch also etches and removes the interfacial layer not under the patterned gate layer.

10. The method of claim 1, wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer.

11. The method of claim 1, wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer;

and wherein the STIs are not substantially affected by the partial etching of the high-k gate dielectric layer not under the patterned gate layer.

12. The method of claim 1, wherein high-k gate dielectric layer has a thickness of from about 20 to 100 Å

; and

the gate ARC layer has a thickness of from about 100 to 500 Å

.

13. The method of claim 1, wherein high-k gate dielectric layer has a thickness of from about 30 to 50 Å

; and

the gate ARC layer has a thickness of from about 200 to 400 Å

.

14. The method of claim 1, wherein high-k gate dielectric layer has a thickness of from about 10 to 50 Å

; and

the gate ARC layer has a thickness of from about 100 to 500 Å

.

15. The method of claim 1, wherein high-k gate dielectric layer has a thickness of from about 20 to 50 Å

; and

the gate ARC layer has a thickness of from about 200 to 400 Å

.

16. The method of claim 1, wherein the gate layer is formed to a thickness of from about 400 to 3000 Å

thick and is partially etched by the Ar sputter or the F-based-chemistry plasma etch to form a partially etched gate layer having a thickness of from about 300 to 2000 Å

.

17. The method of claim 1, wherein the gate layer is formed to a thickness from about 1200 to 1800 Å

thick and is partially etched by the Ar sputter or the F-based-chemistry plasma etch to form a partially etched gate layer having a thickness of from about 1000 to 1500 Å

.

18. The method of claim 1, wherein the patterned gate ARC layer is removed from over the patterned gate layer before the Ar sputter or the F-based-chemistry plasma etch.

19. The method of claim 1, wherein the patterned gate ARC layer is removed from over the patterned gate layer before the Ar sputter or the F-based-chemistry plasma etch and leaving a rough exposed upper surface of the patterned gate layer.

20. A method of forming a gate electrode, comprising the steps of:

providing a substrate having a high-k gate dielectric layer formed thereover;

forming a gate layer over the high-k gate dielectric layer;

forming a gate ARC layer over the gate layer;

patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;

removing the patterned ARC layer from over the patterned gate layer;

subjecting the structure to an Ar sputter or an F-based-chemistry plasma etch to partially etch the high-k gate dielectric layer not under the patterned gate layer and to form a smooth exposed upper surface of the patterned gate layer; and

then removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer using an H₂SO₄ wet etch chemistry process to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

21. The method of claim 20, wherein the substrate is a silicon substrate;

the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSiO₄, HfSiO₄, LaSiO₄, YSiO₄, ZrSi_xO_y and HfSi_xO_y;

the gate layer is comprised of a material selected from the group consisting of polysilicon, polycide and a poly-Si/poly-Ge stack structure; and

the gate ARC layer is comprised of a material selected from the group consisting of SiN, SiON, silicon oxide, organic ARC and an organic ARC/SiON stack structure.

22. The method of claim 20, wherein the substrate is a silicon substrate;

the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSi_xO_y and HfSi_xO_y;

the gate layer is comprised of polysilicon; and

the gate ARC layer is comprised of an organic ARC/SiON stack structure.

23. The method of claim 20, wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters:

Ar;

from about 20 to 500 sccm;

power;

from about 200 to 2000 Watts;

temperature;

from about 0 to 100°

C.;

pressure;

from about 5 to 50 mTorr; and

time;

from about 5 to 30 seconds.

24. The method of claim 20, wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters:

Ar;

from about 100 to 200 sccm;

power;

from about 300 to 500 Watts;

temperature;

from about 80 to 90°

C.;

pressure;

from about 20 to 50 mTorr; and

time;

from about 5 to 10 seconds.

25. The method of claim 20, wherein the H₂SO₄ wet etch chemistry process is conducted at the following parameters:

H₂SO₄;

from about 2 to 20% by volume;

temperature;

from about 25 to 130°

C.; and

time;

from about 10 to 30 seconds.

26. The method of claim 20, wherein the H₂SO₄ wet etch chemistry process is conducted at the following parameters:

H₂SO₄;

from about 2 to 5% by volume;

temperature;

from about 25 to 50°

C.; and

time;

from about 10 to 20 seconds.

27. The method of claim 20, wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween.

28. The method of claim 20, wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween;

and wherein the Ar sputter or the F-based-chemistry plasma etch also etches and removes the interfacial layer not under the patterned gate layer.

29. The method of claim 20, wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer.

30. The method of claim 20, wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer;

and wherein the STIs are not substantially affected by the H₂SO₄ wet etch chemistry process.

31. The method of claim 20, wherein high-k gate dielectric layer has a thickness of from about 20 to 100 Å

; and

the gate ARC layer has a thickness of from about 100 to 500 Å

.

32. The method of claim 20, wherein high-k gate dielectric layer has a thickness of from about 30 to 50 Å

; and

the gate ARC layer has a thickness of from about 200 to 400 Å

.

33. The method of claim 20, wherein the gate layer is partially etched by the Ar sputter or the F-based-chemistry plasma etch to form a partially etched gate layer having a thickness of from about 300 to 2000 Å

.

34. The method of claim 20, wherein the gate layer is partially etched by the Ar sputter or the F-based-chemistry plasma etch to form a partially etched gate layer having a thickness of from about 1000 to 1500 Å

.

35. The method of claim 20, wherein the removal of the patterned gate ARC layer from over the patterned gate layer leaves a rough exposed upper surface of the patterned gate layer.

36. The method of claim 20, wherein high-k gate dielectric layer has a thickness of from about 10 to 50 Å

; and

the gate ARC layer has a thickness of from about 100 to 500 Å

.

37. The method of claim 20, wherein high-k gate dielectric layer has a thickness of from about 20 to 50 Å

; and

the gate ARC layer has a thickness of from about 200 to 400 Å

.