Gated isolation structure for imagers

• US 6,818,930 B2
• Filed: 11/12/2002
• Issued: 11/16/2004
• Est. Priority Date: 11/12/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra, Rhodes, Howard
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US10/291,728
• Publication Number:
  US 20040092054A1
• Time in Patent Office: 735 Days
• Field of Search: 257/215-223, 257/231, 257/249, 257/291, 257/292, 257/396, 257/446, 257/288, 257/461, 257/347, 257/233, 257/432, 257/447, 257/467, 438/60
• US Class Current: 257/215
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

Claims

1. An image sensor comprising:

a pixel comprising a photosensitive region;

an isolation region adjacent said pixel; and

an isolation gate provided over said isolation region for accumulating charge in a region adjacent to said isolation.

2. The sensor of claim 1 wherein said pixel further comprises at least one transistor gate for transferring photoelectric charges from said photosensitive region and wherein said isolation gate is of the same conductivity type as said at least one transistor gate.

3. The sensor of claim 1 wherein said photosensitive region, comprises a p-type conductivity substrate, an n-type conductivity photodiode region, and a p-type conductivity surface region.

4. The sensor of claim 3 wherein said isolation gate extends over at least a portion of a region between said photosensitive region of said pixel and said isolation region and said isolation gate is biased to accumulate holes in said region between said photosensitive region of said pixel and said isolation region.

5. The sensor of claim 3 wherein said isolation gate is biased to expand a region between said photosensitive region of said pixel and said isolation region.

6. The sensor of claim 1 wherein said isolation gate is biased to ground.

7. The sensor of claim 1 wherein said isolation gate is biased to a negative potential.

8. The sensor of claim 1 wherein said isolation gate is biased to provide electrical isolation between adjacent pixels.

9. The sensor of claim 1 wherein said isolation gate has an n-type conductivity.

10. The sensor of claim 9 wherein said n-type isolation gate is biased to a negative reference voltage.

11. The sensor of claim 1 wherein said isolation gate has a p-type conductivity.

12. The sensor of claim 11 wherein said p-type isolation gate is biased to a positive voltage.

13. The sensor of claim 12 wherein said positive voltage is about 5 volts or less.

14. The sensor of claim 1 wherein said isolation region comprises a trench having a depth of 5000 Å

or less.

15. The sensor of claim 1 wherein said isolation region does not comprise a trench.

16. The sensor of claim 1 wherein said isolation region comprises an active area.

17. The sensor of claim 1 wherein said photosensitive region comprises a photosensor.

18. The sensor of claim 1 wherein said photosensitive region comprises a photodiode.

19. The sensor of claim 1 wherein said photosensitive region comprises a photogate.

20. The sensor of claim 1 wherein said photosensitive region comprises a photoconductor.

21. The sensor of claim 1 wherein said image sensor comprises a CMOS image sensor.

22. The sensor a claim 21 wherein said CMOS image sensor comprises a three transistor (3T) CMOS image sensor.

23. The sensor of claim 21 wherein said CMOS image sensor comprises a four transistor (4T) CMOS image sensor.

24. The sensor of claim 1 wherein said image sensor comprises a CCD image sensor.

25. An image sensor, said image sensor comprising:

an active layer of a first conductivity type formed within a substrate;

at least one transistor gate formed over a portion of said active layer;

a photosensor formed adjacent to said transistor gate;

an isolation region formed in said active layer adjacent to said photosensor, wherein said isolation region comprises a portion of said active layer; and

an isolation gate formed over at least a portion of said isolation region.

26. The sensor of claim 25 wherein said photosensor comprises a p-n-p junction region formed under said at least one transistor gate, said p-n-p junction region comprising a surface layer of said first conductivity type overlying a photosensitive region of a second conductivity type, said photosensitive region overlying said active layer of said first conductivity type.

27. The sensor of claim 26 wherein said isolation region is formed in said active layer adjacent to said p-n-p junction region.

28. The sensor of claim 25 wherein said photosensor comprises a photodiode.

29. The sensor of claim 25 wherein said photosensor comprises a photogate.

30. The sensor of claim 25 wherein said photosensor comprises a photoconductor.

31. The sensor of claim 25 wherein said photosensor comprises a p-n-p diode.

32. The sensor of claim 25 wherein said photosensor comprises a buried diode.

33. The sensor of claim 25 wherein said isolation region comprises a trench having a depth of 4000 Å

or less.

34. The sensor of claim 25 wherein said isolation region does not comprise a trench.

35. The sensor of claim 25 wherein said transistor gate has an n-type conductivity.

36. The sensor of claim 25 wherein said isolation gate has a p-type conductivity.

37. The sensor of claim 26 wherein said isolation gate is biased to accumulate holes in a connection region formed between said p-n-p junction region and said isolation region.

38. The sensor of claim 25 wherein said isolation gate is biased to a ground potential.

39. The sensor of claim 36 wherein said isolation gate is biased to a negative voltage potential.

40. The sensor of claim 37 wherein said isolation gate is biased to a positive voltage potential.

41. The sensor of claim 25 wherein said isolation gate assists in isolating said photosensor from an adjacent active area containing another photosensor.

42. The sensor of claim 25 wherein said isolation region comprises a trench having sidewalls, said trench being filled with an insulating material.

43. The sensor of claim 42 wherein said isolation gate is biased to create positively charged holes along a sidewall of said trench.

44. The sensor of claim 25 wherein said transistor gate is a transfer gate.

45. A processor based system comprising the sensor of claim 25.

46. A CMOS image sensor comprising:

a pixel for receiving incident photo energy and converting it into an electrical signal;

said pixel comprising;

a photosensitive area for accumulating photo-generated charge;

a floating diffusion region adjacent a side of said photosensitive area for receiving charge from said photosensitive area;

a read out circuit comprising at least an output transistor for reading out charge from said floating diffusion region;

an isolation region formed around at least a portion of said pixel; and

an isolation gate formed over at least a portion of said isolation region, wherein said isolation gate substantially surrounds said photosensitive area.

47. The image sensor of claim 46 wherein said isolation gate is of a same conductivity type as a gate of said output transistor.

48. The image sensor of claim 46 wherein said isolation gate has an n-type conductivity.

49. The image sensor of claim 46 wherein said isolation gate has a p-type conductivity.

50. The image sensor of claim 46 wherein said isolation gate is biased to a ground potential.

51. The image sensor of claim 48 wherein said isolation gate is biased to a negative potential.

52. The image sensor of claim 49 wherein said isolation gate is biased to a positive potential.

53. The image sensor of claim 46 wherein said isolation region comprises a trench having a depth of 4000 Å

or less.

54. The image sensor of claim 46 wherein said isolation region does not comprise a trench.

55. The image sensor of claim 46 wherein said isolation region is an active area.

56. The image sensor of claim 46 wherein said isolation gate is formed over a substantial portion of said isolation region.

57. The image sensor of claim 46 wherein said photosensitive area comprises a photodiode.

58. The image sensor of claim 46 wherein said photosensitive area comprises a photogate.

59. The image sensor of claim 46 wherein said photosensitive area comprises a photoconductor.

60. The image sensor of claim 57 wherein said photosensitive area comprises a p-n-p diode.

61. The image sensor of claim 57 wherein said photosensitive area comprises a buried diode.

62. An image sensor comprising:

a semiconductor substrate having a plurality of image sensor pixels formed thereon;

each of said pixels comprising a photosensitive region and a floating diffusion region;

an active area formed between adjacent pixels; and

at least one isolation gate formed over a portion of said active area, wherein said isolation gate is biasable for accumulating holes in a portion of said active area between said photosensitive region and said isolation gate.

63. The sensor of claim 62 wherein said pixel comprises at least one transistor gate for transferring photoelectric charges and wherein said isolation gate is of the same conductivity type as said at least one transistor gate.

64. The sensor of claim 62 wherein said photosensitive region comprising a p-type conductivity substrate, an n-type conductivity photodiode region, and a p-type conductivity surface region.

65. The sensor of claim 62 wherein said isolation gate is biased to ground.

66. The sensor of claim 62 wherein said isolation gate is biased to a negative potential.

67. The sensor of claim 62 wherein said isolation gate is biased to provide electrical isolation between adjacent pixels.

68. The sensor of claim 62 wherein said isolation gate has an n-type conductivity.

69. The sensor of claim 68 wherein said n-type isolation gate is biased to a negative reference voltage.

70. The sensor of claim 62 wherein said isolation gate has a p-type conductivity.

71. The sensor of claim 70 wherein said p-type isolation gate is biased to a positive voltage.

72. The sensor of claim 71 wherein said positive voltage is about 5 volts or less.

73. An integrated circuit comprising:

a semiconductor substrate having a plurality of image sensor pixels formed thereon;

each of said pixels comprising a photosensitive region and a floating diffusion region;

an isolation region formed between adjacent pixels;

at least one isolation gate formed over a portion of said isolation region, said isolation gate being biasable to a constant voltage such that the isolation gate constantly reverse biases the isolation region.

74. The circuit of claim 73 wherein said isolation region comprises a trench having a depth of 4000 Å

or less.

75. The circuit of claim 73 wherein said isolation region does not comprise a trench.

76. The circuit of claim 73 wherein said isolation region is an active area.

77. The circuit of claim 73 wherein said isolation region comprises an insulation filled trench having sidewalls.

78. The circuit of claim 77 wherein said voltage causes holes to accumulate in a region between said photosensitive region and said sidewalls of said trench.

79. The circuit of claim 73 wherein said pixels further comprise a transfer gate between said photosensitive region and said floating diffusion region.

80. The circuit of claim 79 wherein said transfer gate and said isolation gate are of the same conductivity type.

81. The circuit of claim 73 wherein said isolation gate has an n-type conductivity.

82. The circuit of claim 73 wherein said isolation gate has a p-type conductivity.

83. The circuit of claim 73 wherein said constant voltage is a ground potential.

84. The circuit of claim 81 wherein said constant voltage is a negative potential.

85. The circuit of claim 82 wherein said constant voltage is a positive potential.

86. The circuit of claim 79 wherein said isolation gate surrounds a substantial portion of said pixels but does not contact said transfer gate or said floating diffusion region.

87. An image sensor comprising:

a substrate having a doped layer of a first conductivity type;

an array of pixel sensor cells formed in said doped layer;

an isolation region formed between each pixel sensor cell; and

an isolation gate formed over a substantial portion of said isolation region, said isolation gate being formed over at least a portion of said doped layer.

88. An integrated circuit comprising:

a semiconductor substrate having an image sensor pixel formed thereon;

said pixel comprising at least one transfer gate disposed over and between a floating diffusion region and a photosensitive active region;

an isolation channel formed in said substrate and between said pixel and an adjacent pixel; and

an isolation gate formed over said isolation channel, whereby said isolation gate extends around substantially all of said photosensitive active region, the isolation gate being biasable by a voltage such that the isolation gate biases the isolation channel.

89. The integrated circuit of claim 88 wherein the isolation region comprises a filled trench, said filled trench being less than about 0.7 microns deep.

90. The integrated circuit of claim 88 wherein said transfer gate and said isolation gate are formed of a same conductivity type.

91. The integrated circuit of claim 88 wherein said voltage is a ground potential.

92. The integrated circuit of claim 88 wherein said isolation gate is formed of an n-type conductivity material.

93. The integrated circuit of claim 88 wherein said voltage is a negative potential.

94. The integrated circuit of claim 88 wherein said isolation gate is formed of a p-type conductivity material.

95. The integrated circuit of claim 94 wherein said voltage is a positive potential.

96. The integrated circuit of claim 88 wherein said isolation gate is biased to accumulate holes in a connection region between said photosensitive active region and said isolation region.