Trench MOSFET with increased channel density

• US 6,818,946 B1
• Filed: 08/28/2000
• Issued: 11/16/2004
• Est. Priority Date: 08/28/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US09/649,368
• Time in Patent Office: 1,541 Days
• Field of Search: 257/330, 257/332, 257/923, 438/212, 438/270, 438/271
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/923 with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66,68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66,68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66,68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66,68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56). A metal electrode layer (82) is formed above the major surface (56) where a portion is formed inside the trench (60) making source contact to the source regions (66,68) inside the trench (60) along the vertical wall (84) of the trench (60).

Claims

1. A semiconductor device, comprising:

a semiconductor material body having a trench extending from a major surface to a depth within the semiconductor material body;

a gate structure disposed within the trench;

an interlayer dielectric (ILD) region disposed within the trench above the gate structure and below the major surface of the semiconductor material body; and

a source contact region disposed vertically along a sidewall of the trench above the gate structure and below the major surface of the semiconductor material body.

2. The semiconductor device of claim 1, wherein the semiconductor material body includes:

a substrate region of the first conductivity type disposed in the semiconductor material body; and

a base region of the second conductivity type extending from the major surface of the semiconductor material body.

3. The semiconductor device of claim 2, wherein the semiconductor material body further includes an epi region of the first conductivity type disposed between the substrate region and the base region, wherein the first conductivity type of the epi region has a lower dopant concentration than the first conductivity type of the substrate region.

4. The semiconductor device of claim 2, further including a doped region having the second conductivity type formed within the base region, wherein the second conductivity type of the doped region has a higher dopant concentration than the second conductivity type of the base region.

5. The semiconductor device of claim 1, further including a gate oxide layer formed between the gate structure and the trench.

6. The semiconductor device of claim 1, further including a metal electrode layer, wherein a portion of the metal electrode layer extends within the trench and onto the ILD region making electrical contact inside the trench.

7. A semiconductor device having a major surface, comprising:

a first region of a first conductivity type;

a second region of a second conductivity type disposed above the first region;

a trench extending vertically from the major surface of the semiconductor device through the second region;

a third region of the first conductivity type disposed in the second region having a vertical component along the trench, wherein the vertical component of the third region along the trench is greater than a horizontal component of the third region; and

a metal electrode layer formed below the major surface making contact to the third region inside the trench along the vertical component of the third region of the semiconductor device.

8. The semiconductor device of claim 7, further including a fourth region of the first conductivity type disposed between the first region and the second region such that the trench extends partially into the fourth region.

9. The semiconductor device of claim 7, further including a gate structure having a top surface, wherein the gate structure is disposed within the trench where the top surface of the gate structure is below the major surface of the semiconductor device.

10. The semiconductor device of claim 9, further including an ILD region disposed within the trench above the top surface of the gate structure, and below the major surface of the semiconductor device.

11. The semiconductor device of claim 7, further including a doped region formed within the second region, and having the second conductivity type, wherein the second conductivity type of the doped region has a higher dopant concentration than the second conductivity type of the second region.

12. The semiconductor device of claim 9, further including a gate oxide layer formed between the gate structure and the trench.

13. The semiconductor device of claim 10, wherein a portion of the metal electrode layer extends within the trench onto the ILD region.

14. A semiconductor device having a major surface, comprising:

a semiconductor material body having a trench extending vertically from the major surface to a depth within the semiconductor material body;

a source contact region of the first conductivity type disposed vertically along the trench; and

a metal electrode layer formed below the major surface making source contact vertically with the source contact region inside the trench of the semiconductor device.

15. The semiconductor device of claim 14, wherein the vertical length of the source contact region along the trench is greater than a horizontal width of a source region.

16. The semiconductor device of claim 15, wherein a ratio of the vertical length of the source contact region to the horizontal width of the source region is greater than 3:

1.

17. A semiconductor device, comprising:

a semiconductor substrate formed with a trench;

a conductive material disposed within the trench to control a current through the semiconductor device; and

a doped region formed in the semiconductor substrate adjacent to the trench to conduct the current, where the doped region is electrically contacted along a sidewall of the trench.

18. The semiconductor device of claim 17, further comprising a dielectric material disposed in the trench and having a first surface adjacent to the conductive material and a second surface below a major surface of the semiconductor substrate.