Buried gate-field termination structure

• US 6,818,947 B2
• Filed: 09/19/2002
• Issued: 11/16/2004
• Est. Priority Date: 09/19/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E., Kocon, Christopher B., Ridley, Sr., Rodney S., Dolny, Gary M., Kraft, Nathan Lawrence, Skurkey, Louise E.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US10/247,464
• Publication Number:
  US 20040056302A1
• Time in Patent Office: 789 Days
• Field of Search: 257/302-339
• US Class Current: 257/330
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a power semiconductor device 10, a continuous trench has an outer circumferential portion 58 that includes a field plate and inner portions 28 that carry include one or more gate runners 34 to that the gate runners and the field plate are integral with each other. The trench structure 58, 28 is simpler to form and takes up less surface space that the separate structures of the prior art. The trench is lined with an insulator and further filled with conductive polysilicon and a top insulator.

Claims

1. A switchable semiconductor power device of the type which controls current conduction based on field effect principles, comprising:

a semiconductor layer having a transistor region including a source/drain formation and a termination region surrounding the transistor region, said termination region including an outer periphery corresponding to an edge of the device; and

a single conductor, configured for connection to a gate voltage supply, including first and second conductor portions with the first conductor portion formed in a trench and being positioned in the transistor region to control current flow through the source/drain formation and the second conductor portion positioned in the termination region, the second conductor portion;

including a contact for connection to the gate voltage supply; and

including a feed comprising conductive material formed in a trench extending along the outer periphery and around the transistor region, said feed electrically connecting the contact with the first conductor portion; and

acting as a field plate to extend the device breakdown voltage in the termination region; and

an isolation trench extending into the semiconductor layer and positioned between the edge of the device and the second conductor portion.

2. The device of claim 1 further comprising a plurality of additional source/drain formations each configured with the first conductor portion in and about a trench region to provide a voltage-switchable conduction channel for controlling current flow through the semiconductor layer.

3. The device of claim 1 wherein the transistor region comprises a vertical MOSFET device.

4. A method for manufacturing a semiconductor device, comprising:

providing on a layer of semiconductor material an active region and a termination periphery region surrounding the active region with a trenched transistor formation in the active region;

forming a trenched gate runner in the termination region along the active region; and

forming first and second conductor regions such that said first and second conductor regions are electrically connected to form a continuous conductor with multiple regions and said first conductor region is in said trenched transistor formation and said second conductor region is said trenched gate runner such that said second conductor also acts as a field plate termination;

wherein

the trenched gate runner extends further into the layer of semiconductor material than the trenched transistor formation.

5. A method for manufacturing a semiconductor device, comprising:

providing on a layer of semiconductor material an active region and a termination periphery region surrounding the active region with a trenched transistor formation in the active region;

forming a trenched gate runner in the termination region along the active region, the trenched transistor formation including a gate conductor formed simultaneously with the gate runner by deposition of polysilicon; and

forming first and second conductor regions such that said first and second conductor regions are electrically connected to form a continuous conductor with multiple regions and said first conductor region is in said trenched transistor formation and said second conductor region is said trenched gate runner such that said second conductor also acts as a field plate termination

the trenched transistor formation including a gate conductor formed simultaneously with the gate runner by deposition of polysilicon

6. A semiconductor structure comprising:

a layer of semiconductor material having an active device region and a peripheral region surrounding the active region;

a transistor device formed in the active region including a plurality of source regions on one surface and drain region on the opposite surface;

a trench having an outer annular portion disposed in the peripheral region and enclosing the transistor device, the walls and the floor of the outer annular portion lined with an insulator and the outer annular portion filled with conductive material for forming a field plate around the transistor regions; and

a plurality of elongated inner runners extending in the same direction across the one surface with the source regions and intersecting the outer annular portion at opposite ends of the runners, the runners having their floors and their walls lined with a gate insulating material and the runners filled with a conductor

to form a gate structure in the transistor region to control current between the source regions and the drain.

7. The semiconductor of claim 6, wherein the conductor material comprises conductive polysilicon.

8. The semiconductor of claim 7, further comprising a layer of metal on the conductive polysilicon.

9. The semiconductor of claim 7 wherein the insulator in the outer annular portion is thicker than the gate insulator in the runners.

10. The semiconductor of claim 7 wherein a common layer of conductive polysilicon fills the trench.