Ball grid array package with shielding

• US 6,818,978 B1
• Filed: 11/19/2002
• Issued: 11/16/2004
• Est. Priority Date: 11/19/2002
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: ASAT Company Limited
• Inventors: Fan, Chun Ho
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US10/299,622
• Time in Patent Office: 728 Days
• Field of Search: 257/685, 257/686, 257/777, 257/784, 257/723, 257/786, 257/787, 257/737, 257/738, 257/508, 257/659, 257/660, 257/773
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit package is provided. The package has a substrate having first and second surfaces and a plurality of conductive traces therebetween. A stacked semiconductor die apparatus is coupled to the substrate. The stacked semiconductor die apparatus includes a first semiconductor die, a second semiconductor die stacked on the first semiconductor die and a shield disposed between the first and second semiconductor dice. A plurality of wire bonds connect the first and second semiconductor dice to ones of the conductive traces of the substrate. At least one encapsulating material encapsulates the wire bonds, the first semiconductor die and the second semiconductor die. A ball grid array is disposed on the second surface of the substrate such that bumps of the ball grid array are in electrical connection with ones of the conductive traces.

Claims

1. An integrated circuit package comprising:

a substrate having first and second surfaces and a plurality of conductive traces therebetween;

a stacked semiconductor die apparatus coupled to said substrate, said stacked semiconductor die apparatus comprising a first semiconductor die, a second semiconductor die stacked on said first semiconductor die and a metallic shield disposed between the first and second semiconductor dice, the first semiconductor die being mounted on said first surface of said substrate, the metallic shield being larger than both the first semiconductor die and the second semiconductor die for shielding radio frequency interference signals or electromagnetic interference signals to or from the first semiconductor die, the stacked semiconductor die apparatus further comprising a spacer fixed to said first semiconductor die, an opposing side of said spacer being fixed to said metallic shield;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die; and

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces;

wherein

said second semiconductor die is fixed directly to said metallic shield.

2. The integrated circuit package according to claim 1, wherein said first and second semiconductor dice are spaced apart by at least one spacer and by said metallic shield.

3. An integrated circuit package comprising:

a substrate having first and second surfaces and a plurality of conductive traces therebetween;

a stacked semiconductor die apparatus coupled to said substrate, said stacked semiconductor die apparatus comprising a first semiconductor die, a second semiconductor die stacked on said first semiconductor die and a metallic shield disposed between the first and second semiconductor dice, said first semiconductor die being mounted on said first surface of said substrate, the metallic shield being larger than both the first semiconductor die and the second semiconductor die for shielding radio frequency interference signals or electromagnetic interference signals to or from the first semiconductor die;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die; and

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces;

wherein

said stacked semiconductor die apparatus further comprises at least one spacer fixed to said first surface of said substrate, said metallic shield being mounted on said at least one spacer such that said metallic shield is spaced from said first semiconductor die.

4. The integrated circuit package according to claim 3, wherein said at least one metallic shield comprises a ring spacer surrounding said first semiconductor die.

5. The integrated circuit package according to claim 3, wherein said second semiconductor die is mounted to said metallic shield such that said first and second semiconductor dice are spaced apart and stacked.

6. An integrated circuit package comprising:

a substrate having first and second surfaces and a plurality of conductive traces therebetween;

a stacked semiconductor die apparatus coupled to the substrate, the stacked semiconductor die apparatus comprising a first semiconductor die mounted on the first surface of the substrate, a second semiconductor die stacked on said first semiconductor die and a metallic shield disposed between the first and second semiconductor dice, the metallic shield being mounted on a pair of spacers mounted on said substrate on either side of said first semiconductor die, the pair of spacers being mounted on said first surface of said substrate, such that the metallic shield is spaced from the first semiconductor die;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die; and

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces.

7. An integrated circuit package comprising:

a substrate having first and second surfaces and a plurality of conductive traces therebetween;

a stacked semiconductor die apparatus coupled to the substrate, the stacked semiconductor die apparatus comprising a first semiconductor die mounted on the first surface of the substrate, a second semiconductor die stacked on said first semiconductor die, a metallic shield disposed between the first and second semiconductor dice, the metallic shield being mounted on a plurality of spacers mounted on said substrate, around said first semiconductor die, said plurality of spacers being mounted on said first surface of said substrate, such that the metallic shield is spaced from the first semiconductor die;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die; and

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces.

8. An integrated circuit package comprising:

a substrate having first and second surfaces, a plurality of conductive traces therebetween and a cavity therein;

a stacked semiconductor die apparatus coupled to said substrate, said stacked semiconductor die apparatus comprising a first semiconductor die, a second semiconductor die stacked on said first semiconductor die and a metallic shield disposed between the first and second semiconductor die, a portion of said metallic shield being mounted on said first surface of said substrate such that said metallic shield being is disposed over said cavity, and said first semiconductor die being mounted to a first surface of said metallic shield whereby said first semiconductor die is disposed in said cavity, the metallic shield being larger than both the first semiconductor die and the second semiconductor die for shielding radio frequency interference signals or electromagnetic interference signals to or from the first semiconductor die;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die; and

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces;

wherein

said second semiconductor die is mounted directly on an opposing surface of said metallic shield.

9. The integrated circuit package according to claim 8, wherein said encapsulating material is a glob-top material.

10. An integrated circuit package comprising:

a substrate having first and second surfaces, a plurality of conductive traces therebetween and a cavity therein;

a stacked semiconductor die apparatus coupled to said substrate, said stacked semiconductor die apparatus comprising a first semiconductor die, a second semiconductor die stacked on said first semiconductor die and a metallic shield disposed between the first and second semiconductor dice, a portion of said metallic shield being mounted on said first surface of said substrate such that said metallic shield being is disposed over said cavity, and said first semiconductor die being mounted to a first surface of said metallic shield whereby said first semiconductor die is disposed in said cavity, the metallic shield being larger than both the first semiconductor die and the second semiconductor die for shielding radio frequency interference signals or electromagnetic interference signals to or from the first semiconductor die;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die; and

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces;

wherein

said second semiconductor die is mounted on an opposing surface of said metallic shield, and wherein said at least one encapsulating material comprises a first encapsulant surrounding the first semiconductor die, and a second encapsulant surrounding the second semiconductor die.

11. The integrated circuit package according to claim 10, wherein the first encapsulant material is different from the second encapsulant material.

12. An integrated circuit package comprising:

a substrate having first and second surfaces and a plurality of conductive traces therebetween, the substrate further having a cavity therein;

a stacked semiconductor die apparatus coupled to said substrate, said stacked semiconductor die apparatus comprising a first semiconductor die, a second semiconductor die stacked on said first semiconductor die and a metallic shield disposed between the first and second semiconductor dice, a portion of said metallic shield being mounted on said first surface of said substrate such that said metallic shield is disposed over said cavity, and said first semiconductor die is mounted to a first surface of said metallic shield whereby said first semiconductor die is disposed in said cavity;

a second metallic shield coupled to said second surface of said substrate and covering said cavity;

a plurality of wire bonds connecting said first and second semiconductor dice to ones of said conductive traces of said substrate;

at least one encapsulating material for encapsulating said wire bonds, said first semiconductor die and said second semiconductor die;

a ball grid array disposed on said second surface of said substrate, bumps of said ball grid array being in electrical connection with ones of said conductive traces, said second semiconductor die is mounted on an opposing surface of said metallic shield.

13. The integrated circuit package according to claim 12, wherein said substrate further comprises a plurality of solder pads electrically connected to said ones of said conductive traces, said bumps of said ball grid array being disposed on said solder pads.

14. The integrated circuit package according to claim 13, wherein said bumps of said ball grid array comprise a first solder on each of said solder pads and a second solder disposed on said first solder.

15. The integrated circuit package according to claim 14, wherein said first solder comprises a eutectic solder and said second solder comprises a high lead solder.