Customizable and programmable cell array

• US 6,819,136 B2
• Filed: 06/03/2003
• Issued: 11/16/2004
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/452,049
• Publication Number:
  US 20030206036A1
• Time in Patent Office: 532 Days
• Field of Search: 326/41, 326/38, 326/101, 326/37-40
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Claims

1. A logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein;

at least some of said programmable cells are programmable by means of electrical signals supplied thereto; and

at least some of said customized interconnections are customized by lithography.

2. A logic array according to claim 1, wherein said customized interconnections comprise at least one metal layer comprising repeated subpatterns.

3. A logic array according to claim 1, wherein each of said programmable cells also comprises at least one multiplexer, and wherein at least some of said multiplexers are configured to perform a logic operation.

4. A logic array according to claim 1, wherein said programmable logic cell includes at least one inverter selectably connected to at least one of said multiplicity of outputs.

5. A logic array according to claim 1, wherein said programmable cell comprises at least one flip-flop.

6. A logic array according to claim 1, wherein the functionality of at least some of said programmable cells as being either logic or memory is determined by a configuration of said customized interconnections.

7. A logic array according to claim 1, wherein said lithography utilizes direct write e-beam technology.

8. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said multiplicity of inputs and multiplicity of outputs;

said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various ones of said inputs and outputs in a customized manner.

9. A semiconductor device according to claim 8, wherein said logic cells also comprise at least one multiplexer, and wherein said multiplexer is configured to perform a logic function by said metal connection layers.

10. A semiconductor device according to claim 9, wherein said logic function is one of the following logic functions:

NAND, NOR, AND, OR, and XOR.

11. A semiconductor device according to claim 8, wherein said logic array comprises a clock tree.

12. A semiconductor device according to claim 8, wherein said logic array comprises a scan chain.

13. A semiconductor device according to claim 8, wherein said standard metal layer comprises at least one metal strip, and wherein said metal strip has at least two vias overlying it.

14. A semiconductor device according to claim 8, wherein said metal connection layers comprise at least one custom via layer and at least one custom metal layer.

22. A semiconductor device according to claim 10, wherein said clock tree comprises metal strips that are part of said standard metal layer.

15. A semiconductor device comprising:

a logic array comprising a multiplicity of cells said cells having at least one input and at least one output, each cell including at least one flip-flop;

said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner, said metal connection layers comprising at least one custom via layer and at least one custom metal layer.

16. A semiconductor device according to claim 15, wherein said cell also comprises an inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said at least one input and at least one output.

17. A semiconductor device according to claim 15, wherein said logic array comprises a clock tree.

18. A semiconductor device according to claim 15, wherein said logic array comprises a scan chain.

19. A semiconductor device according to claim 15, wherein said standard metal layer comprises at least one metal strip, and wherein said metal strip has at least two vias overlying it.

20. A semiconductor device according to claim 15, wherein said logic cells also comprise at least one multiplexer, and wherein said multiplexer is configured to perform a logic function by said metal connection layers.

21. A semiconductor device according to claim 20, wherein said logic function is one of the following logic functions:

NAND, NOR, AND, OR, and XOR.

23. A semiconductor device according to claim 17, wherein said clock tree comprises metal strips that are part of said standard metal layer.

24. A semiconductor device according to claim 16, wherein said logic cells also comprise at least one multiplexer, and wherein said multiplexer is configured to perform a logic function by said metal connection layers.

25. A semiconductor device according to claim 15, wherein said logic array also comprises a multiplicity of multiplexers, and wherein at least one of said multiplexers is configured to perform a logic function by said metal connection layers.

26. A semiconductor device according to claim 15, wherein said logic array also comprises a multiplicity of inverters, and wherein each of said inverters has an inverter input and an inverter output, wherein said inverter input and inverter output are part of said various inputs and outputs.

27. A semiconductor device according to claim 17, wherein said logic array also comprises a scan chain.

28. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer;

wherein said at least first, second and third metal layers are part of a set of customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs.

29. A logic array according to claim 28, wherein said logic cells are programmable logic cells.

30. A logic array according to claim 28, wherein said third metal layer comprises at least one third metal layer strip extending generally perpendicular to said second metal layer strips and being connected thereto by a via.

31. A logic array according to claim 28, wherein said third metal layer comprises at least one third metal layer strip extending generally parallel to said second metal layer strips and connecting two coaxial second metal layer strips by vias.

32. A logic array according to claim 28, wherein said second metal layer also comprises a multiplicity of second metal layer strips extending generally parallel to said first axis.

33. A logic array according to claim 28, wherein said third metal layer comprises a repeating pattern.

34. A logic array according to claim 28, wherein each of at least some of said logic cells comprises at least one look-up table.

35. A logic array according to claim 28, wherein the functionality of said customizable logic array as being either logic or memory is determined by a configuration of said customized interconnections.

36. A logic array according to claim 28, wherein each of at least some of said logic cells includes at least one simple logic gate selectably connected to at least one of said multiplicity of outputs.

37. A logic array according to claim 28, wherein each of at least some of said logic cells comprises at least one flip-flop.

38. A logic array according to claim 37, further comprising a clock tree providing clock inputs to at least one of said flip-flops.

39. A logic array according to claim 28, further comprising a custom via layer.

40. A logic array according to claim 39, wherein said custom via layer is defined by the use of direct-write e-beam technology.

41. A logic array according to claim 39, wherein said logic cells, are programmable logic cells.

42. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one multiplexer, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one of said multiplexers is configured to perform a two-input logic function by said metal connection layers.

43. A semiconductor device according to claim 42, wherein said logic cells further comprise at least one inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said multiplicity of inputs and multiplicity of outputs.

44. A semiconductor device according to claim 42, wherein said logic array comprises a clock tree.

53. A semiconductor device according to claim 42, wherein said logic array comprises a scan chain.

54. A semiconductor device according to claim 42, wherein said standard metal layer comprises at least one metal strip, said metal strip having at least two vias overlying it.

55. A semiconductor device according to claim 42, wherein said metal connection layers comprise at least one custom via layer and at least one custom metal layer.

56. A semiconductor device according to claim 42, wherein said two-input logic function is one of the following logic functions:

NAND, NOR, AND, OR, and XOR.

45. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop, said logic array also comprising at least one standard metal layer; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein at least one interconnection within said logic cell is made by said metal connection layers.

46. A semiconductor device according to claim 45, wherein said logic cells also comprise at least one inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said multiplicity of inputs and multiplicity of outputs.

47. A semiconductor device according to claim 45, wherein said logic array comprises a clock tree.

48. A semiconductor device according to claim 45, wherein said logic array comprises a scan chain.

49. A semiconductor device according to claim 45, wherein said standard metal layer comprises at least one metal strip, said metal strip having at least two vias overlying it.

50. A semiconductor device according to claim 45, wherein said metal connection layers comprise at least one custom via layer and at least one custom metal layer.

51. A semiconductor device according to claim 45, wherein said logic array also comprises a multiplicity of multiplexers, wherein at least one of said multiplexers is configured to perform a logic function by said metal connection layers.

52. A semiconductor device according to claim 51, wherein said logic function is one of the following logic functions:

NAND, NOR, AND, OR, and XOR.