Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption

• US 6,819,142 B2
• Filed: 03/13/2003
• Issued: 11/16/2004
• Est. Priority Date: 03/13/2003
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Lammers, Stefan, Viehmann, Hans-Heinrich
• Primary Examiner(s): Le, Don
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/387,733
• Publication Number:
  US 20040178828A1
• Time in Patent Office: 614 Days
• Field of Search: 326/127, 326/86, 326/83, 326/115, 326/104, 326/90
• US Class Current: 326/127
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, output transistor 524) that when the single ended converter 505 is in standby may pull the output of the single ended converter 505 to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.

Claims

1. A circuit comprising:

a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter containing circuitry to convert a differential mode signal into a single ended signal;

an output transistor coupled to the single ended output, the output transistor to set the single ended output to a logic state to a specified value; and

a single ended buffer coupled to the single ended output, the single ended buffer comprising an n-channel transistor coupled to a p-channel transistor.

2. The circuit of claim 1, wherein the CML single ended converter comprises:

a first and a second transistor, each transistor having a second terminal coupled to a voltage supply;

a third and a fourth transistor, the third transistor having a first terminal coupled to a first terminal of the first transistor, the fourth transistor having a first terminal coupled to a first terminal of the second transistor, each transistor having a third terminal coupled to an input signal of the differential mode input, and the third and fourth transistors having their second terminals coupled together; and

a fifth transistor having a second terminal coupled to the voltage supply and a third terminal coupled to the first terminal of the fourth transistor.

3. The circuit of claim 2, wherein the first and second transistors having each of their third terminals coupled together and to the first terminal of the third transistor.

4. The circuit of claim 2, wherein the single ended output of the CML single ended circuit is at a first terminal of the fifth transistor.

5. The circuit of claim 2, wherein the second terminals of the third and fourth transistors is coupled to a first reference current source.

6. The circuit of claim 5, wherein the first terminal of the fifth transistor is coupled to a second reference current source.

7. The circuit of claim 6, wherein the first and second reference current source each comprises:

a sixth transistor having a first terminal coupled to a second terminal of a seventh transistor and third terminal coupled to a reference voltage level; and

the seventh transistor having a third terminals coupled to the reference voltage level.

8. The circuit of claim 7, wherein the first, second, and fifth transistors are P-channel MOSFETs (metal-oxide semiconductor field effect transistors), and the third and fourth are N-channel MOSFETs.

9. The circuit of claim 7, wherein the transistors in the first and second reference current sources are N-channel MOSFETs.

10. The circuit of claim 2, wherein the first terminal is a transistor'"'"'s drain terminal, the second terminal is the transistor'"'"'s source terminal, and the third terminal is the transistor'"'"'s gate terminal.

11. A circuit comprising:

a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter containing circuitry to convert a differential mode signal into a singe ended signal; and

an output transistor coupled to the single ended output, the output transistor to set the single ended output to a logic state to a specified value, wherein the output transistor has a second terminal coupled to a voltage supply and a third terminal coupled to a reference voltage level.

12. The circuit of claim 11, wherein the output transistor creates a conductive path to a voltage supply when the CML single ended converter is in standby.

13. The circuit of claim 11, wherein the voltage supply is at a voltage potential that is within specifications for a high logic value.

24. The circuit of claim 11, wherein the CML single ended converter comprises:

a first and a second transistor, each transistor having a second terminal coupled to a voltage supply;

a third and a fourth transistor, the third transistor having a first terminal coupled to a first terminal of the first transistor, the fourth transistor having a first terminal coupled to a first terminal of the second transistor, each transistor having a third terminal coupled to an input signal of the differential mode input, and the third and fourth transistors having their second terminals coupled together; and

a fifth transistor having a second terminal coupled to the voltage supply and a third terminal coupled to the first terminal of the fourth transistor.

14. A circuit comprising:

a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter containing circuitry to convert a differential mode signal into a single ended signal, wherein the CML single ended converter comprises;

a first and a second transistor, each transistor having a second terminal coupled to a voltage supply;

a third and a fourth transistor, the third transistor having a first terminal coupled to a first terminal of the first transistor, the fourth transistor having a first terminal coupled to a first terminal of the second transistor, each transistor having a third terminal coupled to an input signal of the differential mode input, and the third and fourth transistors having their second terminals coupled together; and

a fifth transistor having a second terminal coupled to the voltage supply and a third terminal coupled to the first terminal of the fourth transistor; and

an output transistor coupled to the single ended output the output transistor to set the single ended output to a logic state to a specified value, wherein the output transistor has a second terminal coupled to substrate ground and third terminal coupled to the third terminal of the fifth transistor.

15. The circuit of claim 14, wherein the output transistor creates a conductive path to substrate ground when the CML single ended converter is in standby.

16. A circuit comprising:

a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter used for converting a differential mode signal into a single ended signal; and

an output regulator circuit coupled to the single ended output, the output regulator circuit used for setting the single ended output to a logic state of a specified value when the CML single ended converter is in standby.

17. The circuit of claim 16, wherein a differential mode signal has two component signals, a first and a second signal, and wherein the CML single ended converter converts the differential mode input into the single ended output by subtracting the second signal of the differential mode input from the first signal of the differential mode input.

18. The circuit of claim 16, wherein the output regulator circuit couples the single ended output to a specified voltage value when the CML single ended converter is in standby.

19. The circuit of claim 18, wherein the output regulator circuit couples the single ended output to a voltage supply that in the range of a high logic value.

20. The circuit of claim 19, wherein the output regulator circuit is a P-channel MOSFET (metal oxide semiconductor field effect transistor) having a drain terminal coupled to the single ended output.

21. The circuit of claim 18, wherein the output regulator circuit couples the single ended output to a substrate ground.

22. The circuit of claim 21, wherein the output regulator circuit is an N-channel MOSFET (metal oxide semiconductor field effect transistor) having a drain terminal coupled to the single ended output.

23. The circuit of claim 16 and further comprising a single ended buffer coupled to the single ended output, wherein the output regulator is used to substantially turn off any static current in the single ended buffer when the CML single ended converter is in standby.

25. A circuit comprising:

a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter containing circuitry to convert a differential mode signal into a single ended signal, the CML single ended converter operable to be placed in a standby mode;

an output transistor coupled to the single ended output, the output transistor to set the single ended output to a logic state to a specified value when the CML single ended converter is in the standby mode; and

a single ended buffer coupled to the single ended output, wherein the output transistor substantially eliminate static current in the single ended buffer when the CML single ended converter is in the standby mode.

26. The circuit of claim 25, wherein the CML single ended converter comprises:

a first and a second transistor, each transistor having a second terminal coupled to a voltage supply,

a third and a fourth transistor, the third transistor having a first terminal coupled to a first terminal of the first transistor, the fourth transistor having a first terminal coupled to a first terminal of the second transistor, each transistor having a third terminal coupled to an input signal of the differential mode input, and the third and fourth transistors having their second terminals coupled together; and

a fifth transistor having a second terminal coupled to the voltage supply and a third terminal coupled to the first terminal of the fourth transistor.

27. A circuit comprising:

a current mirror including a first input node and a second input node, the first and second input nodes operable to receive a differential input signal;

a reference current source coupled to the current mirror, the reference current source operable to be placed in a standby mode;

a transistor with a first terminal coupled to the current mirror and a second terminal coupled to an output node, the output node operable to carry a single ended signal having a logical value based on the differential input signal; and

an output transistor with a current path coupled seen the output node and a power supply node that is held at a supply potential the output transistor operable to set the output node to the supply potential when the reference current source is in the standby mode.

28. The circuit of claim 27 wherein the output transistor comprises an n-channel transistor with a current path coupled between the output node and a ground node that is held at a ground potential.

29. The circuit of claim 28 wherein the transistor comprises a p-channel transistor with a current path coupled between a VDD and the output node, the transistor further including a gate coupled to a gate of the output transistor.

30. The circuit of claim 27 wherein the reference current source includes a reference voltage node, the reference current source operable to be placed in the standby mode when a zero potential is placed on the reference voltage node.

31. The circuit of claim 30 wherein the output transistor comprises an n-channel transistor with a source/drain current path coupled between the output node and a VDD node that is held at a VDD potential, the output further including a gate coupled to the reference voltage node.

32. The circuit of claim 27 and further comprising a single-ended input buffer with an input coupled to the output node.

33. The circuit of claim 32 wherein the single-ended input buffer comprises a CMOS buffer that includes a p-channel transistor with a source coupled to a VDD node and an n-channel transistor with a source coupled to a ground node and a drain coupled to a drain of the p-channel transistor, the p-channel transistor and the n-channel transistor both including a gate coupled to the output node, wherein power supply node comprises one of the ground node or the VDD node.