Level shifter circuit

• US 6,819,159 B1
• Filed: 04/29/2003
• Issued: 11/16/2004
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lencioni, Michael J.
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US10/249,653
• Publication Number:
  US 20040217798A1
• Time in Patent Office: 567 Days
• Field of Search: 327/333, 327/55, 326/62, 326/63, 326/68, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter circuit is disclosed. The level shifter circuit includes a first level shifter circuit and a second level shifter circuit. The first level shifter circuit and the second level shifter circuit are substantially identical with each other. The second level shifter circuit coupled to the first level shifter circuit via a couple of transistor to provide an output and a complementary output, respectively.

Claims

1. A level shifter circuit comprising:

a primary level shifter circuit having a first invertor circuit coupled to said power source via a first p-channel transistor, and a second invertor circuit coupled to said power source via a second p-channel transistor, wherein an output of said first invertor circuit is connected to a gate of said second p-channel transistor, and an output of said second invertor circuit is connected to a gate of said first p-channel transistor, wherein each of the first and second invertor circuits comprises an n-channel transistor and a p-channel transistor; and

a secondary level shifter circuit substantially identical to said primary level shifter circuit, wherein said secondary level shifter circuit is coupled to said primary level shifter circuit via a first driver transistor to provide an output and a second driver transistor to provide an complementary output.

2. The circuit of claim 1, wherein said secondary level shifter circuit includes a third invertor circuit coupled to said power source via a third p-channel transistor, and a second invertor circuit coupled to said power source via a fourth p-channel transistor.

3. The circuit of claim 2, wherein an output of said third invertor circuit is connected to a gate of said fourth p-channel transistor, and an output of said third invertor circuit is connected to a gate of said third p-channel transistor.

4. The circuit of claim 3, wherein one of said first and second driver transistors is connected between said output of said second invertor circuit and output of said third invertor circuit to provide said output.

5. The circuit of claim 4, wherein another one of said first and second driver transistors is connected between said output of said first invertor circuit and output of said fourth invertor circuit to provide said complementary output.

6. The circuit of claim 5, wherein said first and second driver transistors are n-channel transistors.