High power, wide bandwidth operational amplifier

• US 6,819,176 B1
• Filed: 07/11/2003
• Issued: 11/16/2004
• Est. Priority Date: 07/11/2003
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: REMEC, Inc.
• Inventors: Lee, Jerold
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US10/617,463
• Time in Patent Office: 494 Days
• Field of Search: 330/151, 330/124.R, 330/295, 330/292, 330/279, 330/280
• US Class Current: 330/151
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479

Abstract

A high bandwidth operational amplifier architecture has three control loops, which are combined via a voltage-follower-configured field effect transistor. The first control loop is an instantaneous main amplification path and employs positive feedback-based Vgs correction of the output transistor. The second control loop has a bandwidth considerably lower than the first loop and employs negative feedback to correct for long term drift errors. The third control loop, utilizing negative feedback, is a fast path having a bandwidth that overlaps the bandwidth of the first control loop, and corrects for overshoot and undershoot in the main amplification path.

Claims

1. An amplifier architecture comprising:

an input port to which a signal to be amplified is coupled;

an output port from which an amplified signal is derived;

a first amplification path coupled between said input port and said output port and including a first gain stage and an output transistor having a control input terminal coupled to said first gain stage and an output terminal coupled to said output port, said first amplification path being operative to compensate for an offset voltage component in said amplified signal associated with said output transistor;

a second amplification path coupled between said input port and said output port and being operative to correct for long term drift errors in said main amplification path; and

a third amplification path coupled between said input port and said output port and being operative to correct for high frequency transient effects in said main amplification path.

2. The amplifier architecture according to claim 1, wherein said output transistor comprises a source follower-configured field effect transistor.

3. The amplifier architecture according to claim 2, wherein said first amplification path is operative to compensate for a gate-to-source voltage offset component in said amplified signal associated with said field effect transistor.

4. The amplifier architecture according to claim 1, wherein said first amplification path includes a positive feedback loop coupled between said output transistor and said input port, and being operative to feed back a voltage representative of said offset voltage to said input port, so as to be combined with said signal to be amplified and applied to said first gain stage.

5. The amplifier architecture according to claim 4, wherein said second amplification path includes a negative feedback loop coupled between said output port and said input port, and being operative to feed back said amplified signal to said input port, so as to be combined with said signal to be amplified and being applied to a second gain stage, said second gain stage having an output thereof combined with the output of said first gain stage for application to said control electrode of said transistor.

6. The amplifier architecture according to claim 5, wherein said third amplification path includes a fast path coupled between said input port and said output port, and being operative to amplify said input signal by way of a third gain stage, said third gain stage having an output thereof coupled to said output port, so as to be combined with signals amplified by said first and second gain stages and provided at said output terminal of said output transistor.

7. The amplifier architecture according to claim 6, wherein said third amplification path has a bandwidth that overlaps the bandwidth of said first amplification path.

8. The amplifier architecture according to claim 7, wherein said second amplification loop has a bandwidth on the order of decade lower than bandwidths of said first and third amplification loops.

9. An amplifier architecture comprising:

an input port to which a signal to be amplified is coupled;

an output port from which an amplified signal is derived;

a first amplification path coupled between said input port and said output port and including a first gain stage;

an output transistor coupled in voltage follower configuration having a control terminal coupled to said first gain stage and an output terminal coupled to said output port;

a first, positive feedback compensation loop, coupled between said output transistor and said input port, and being operative to feed back a voltage representative of an offset voltage between said control terminal and said output terminal to said input port, so as to be combined with said signal to be amplified and applied to said first gain stage, and compensate for said offset voltage in said amplified signal;

a second, negative feedback loop, coupled between said output port and said input port, and being operative to feed back said amplified signal to said input port, so as to be combined with said signal to be amplified and being applied to a second gain stage, said second gain stage having an output thereof combined with the output of said first gain stage for application to said control electrode of said transistor; and

a third, fast path utilizing negative feedback coupled between said input port and said output port, and being operative to amplify said input signal by way of a third gain stage, said third gain stage having an output thereof coupled to said output port, so as to be combined with signals amplified by said first and second gain stages and provided at said output terminal of said output transistor.

10. The amplifier architecture according to claim 9, wherein said output transistor comprises a source follower-configured field effect transistor.

11. The amplifier architecture according to claim 10, wherein said first, positive feedback loop is operative to compensate for a gate-to-source voltage offset component in said amplified signal associated with said field effect transistor.

12. The amplifier architecture according to claim 9, wherein said third loop has a bandwidth that overlaps the bandwidth of said first loop.

13. The amplifier architecture according to claim 9, wherein said second, negative feedback loop has a bandwidth on the order of decade lower than bandwidths of said first and third loops.

14. A method of controlling the operation of a voltage follower-configured output transistor having a control electrode thereof coupled to receive a signal to be amplified thereby and an output electrode thereof providing an amplified signal, said method comprising the steps of:

(a) coupling a signal to be amplified to a first gain stage an output of which is coupled to said control electrode;

(b) combining a voltage representative of an offset voltage between said control electrode and said output electrode with said signal to be amplified so as to compensate for said offset voltage in said amplified signal;

(c) differentially combining said amplified signal with said signal to be amplified via a second gain stage to produce a difference signal and coupling said difference signal with the output of said first gain stage for application to said control electrode of said transistor; and

(d) coupling said signal to be amplified to a third gain stage an output of which is coupled to said output port and combined thereby with said amplified signal.

15. The method according to claim 14, wherein said output transistor comprises a source follower-configured field effect transistor.

16. The method according to claim 14, wherein said second gain stage has a bandwidth on the order of decade lower than bandwidths of said first and third gain stages.

17. The method according to claim 14, wherein said third gain stage has a bandwidth that overlaps the bandwidth of said first gain stage.

18. The method according to claim 14, wherein said third gain stage provides for instantaneous correction at the combined output of step (d).