API communications for vertex and pixel shaders

• US 6,819,325 B2
• Filed: 03/06/2001
• Issued: 11/16/2004
• Est. Priority Date: 03/07/2000
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles N.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): NGUYEN, HAU H
• Application Number:
  US09/801,079
• Publication Number:
  US 20020003541A1
• Time in Patent Office: 1,351 Days
• Field of Search: 345/559, 345/426, 345/519, 345/552, 345/561, 345/537, 345/538, 345/643, 345/501, 345/522, 709/328
• US Class Current: 345/559
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

Claims

1. A method for communicating between a 3-D graphics API of a host computing system having a main memory stack and a 3-D graphics hardware rendering device having on-chip register storage, comprising:

receiving at least one instruction having at least one graphics data argument by the 3-D API;

formatting said at least one instruction for the register storage of the hardware rendering device;

providing said at least one formatted instruction to the hardware rendering device;

processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware rendering device without accessing the main memory stack of the host computing system;

outputting the result of said processed at least one graphics data argument from said hardware rendering device in accordance with said at least one formatted instruction;

wherein said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the hardware rendering device the fractional portion of said at least one floating point number; and

wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments.

2. The method of claim 1, wherein said formatting includes remapping to the register state of register storage.

3. The method of claim 1, further comprising communicating said at least one instruction directly to said hardware rendering device, thereby bypassing the main memory stack of the host computing system.

4. The method of claim 1, wherein said processing of said at least one graphics data argument includes performing at least one of reading from and writing to the on-chip register storage.

5. The method of claim 1, further comprising storing a register index in the on-chip register storage.

6. The method of claim 5, further comprising accessing the register index stored in the on-chip register storage and finding another register of the register storage to be used incident to carrying out said at least one instruction by said hardware rendering device.

7. The method of claim 1, wherein said hardware rendering device includes a processor and an arithmetic/logic unit that aid in the performance of said processing.

8. The method of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said processing includes processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

9. The method of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said outputting includes outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

10. The method of claim 1, wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by the hardware rendering device.

11. The method of claim 10, wherein said special modifier function performed during said processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

12. A computer-readable medium bearing computer executable instructions for carrying out the method of claim 1.

13. A modulated data signal carrying computer executable instructions for performing the method of claim 1.

14. A computer system, comprising:

a hardware rendering device having on-chip register storage;

a host computing system having a main memory and having stored thereon a 3-D API for communicating at least one instruction having at least one graphics data argument formatted for the register storage of said hardware rendering device to said hardware rendering device;

wherein said hardware rendering device receives said at least one instruction;

wherein the hardware rendering device processes said at least one graphics data argument incident to the performance of said at least one instruction without accessing the main memory of the host computing system and said hardware rendering device outputs the result of the processing;

wherein said at least one instruction is an instruction with at least one floating point number argument and said hardware rendering device outputs the fractional portion of said at least one floating point number; and

wherein said hardware rendering device outputs four fractional portions of corresponding four floating point number arguments.

15. The computer system of claim 14, wherein said at least one graphics data argument is formatted to be remapped to the register state of register storage.

16. The computer system of claim 14, wherein said at least one instruction is communicated directly to said hardware rendering device and the main memory stack of the host computing system is bypassed.

17. The computer system of claim 14, wherein incident to the processing of said at least one graphics data argument, the hardware rendering device performs at least one of reading from and writing to on-chip register storage.

18. The computer system of claim 14, wherein said hardware rendering device further comprises a register index stored in the on-chip register storage.

19. The computer system of claim 18, wherein the register index stored in the on-chip register storage is accessed pursuant to said at least one instruction and another register is located for use in connection with carrying out said at least one instruction.

20. The computer system of claim 14, wherein said hardware rendering device further includes a processor and an arithmetic/logic unit.

21. The computer system of claim 14, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said hardware rendering device processes the plurality of floating point number arguments to calculate a linear interpolation number representative of a linear interpolation between two of the floating point number arguments and wherein said hardware rendering device outputs said linear interpolation number.

22. The computer system of claim 14, wherein said at least one instruction includes a special modifier function to be performed during processing by the hardware rendering device.

23. The computer system of claim 22, wherein said special modifier function performed during said processing by the hardware rendering device is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

24. A method for communicating between a 3-D graphics API of a host computing system having a main memory stack and a hardware procedural shader having on-chip register storage, comprising:

receiving at least one instruction having at least one graphics data argument by the 3-D API;

formatting said at least one instruction for use with the hardware procedural shader;

providing said at least one formatted instruction to said hardware procedural shader;

processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware procedural shader without accessing the main memory stack of the host computing system;

outputting the result of said processed at least one graphics data argument from said hardware procedural shader in accordance with said at least one formatted instruction;

wherein the method is a method for communicating between a 3-D graphics API of a host computing system and a hardware vertex shader with on-chip register storage, and said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the vertex shader the fractional portion of said at least one floating point number; and

wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments.

25. The method of claim 24, further comprising communicating said at least one instruction directly to said hardware procedural shader, thereby bypassing the main memory stack of the host computing system.

26. The method of claim 24, wherein said processing of said at least one graphics data argument includes performing at least one of reading from and writing to the on-chip register storage.

27. The method of claim 24, wherein the method is a method for communicating between a 3-D graphics API of a host computing system and a hardware vertex shader with on-chip register storage, further comprising storing a register index in the on-chip register storage.

28. The method of claim 27, further comprising accessing the register index stored in the on-chip register storage and finding another register of the register storage to be used incident to carrying out said at least one instruction by said hardware vertex shader.

29. The method of claim 24, wherein said hardware procedural shader includes a processor and an arithmetic/logic unit that aid in the performance of said processing.

30. The method of claim 24, wherein the method is a method for communicating between a 3-D graphics API of a host computing system and a hardware pixel shader with on-chip register storage, and said at least one instruction is an instruction with a plurality of floating point number arguments and said processing includes processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

31. The method of claim 24, wherein the method is a method for communicating between a 3-D graphics API of a host computing system and a hardware pixel shader with on-chip register storage, and said at least one instruction is an instruction with a plurality of floating point number arguments and said outputting includes outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

32. The method of claim 24, wherein the method is a method for communicating between a 3-D graphics API of a host computing system and a hardware pixel shader with on-chip register storage, wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by the arithmetic/logic unit of the pixel shader.

33. The method of claim 32, wherein said special modifier function performed during said processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

34. A computer-readable medium bearing computer executable instructions for carrying out the method of claim 24.

35. A modulated data signal carrying computer executable instructions for performing the method of claim 24.

36. A computer system, comprising:

a hardware procedural shader having on-chip register storage;

a host computing system having a main memory having stored thereon a 3-D API for communicating at least one instruction having at least one graphics data argument formatted for said hardware procedural shader to said hardware procedural shader;

wherein said hardware procedural shader receives said at least one instruction;

wherein the hardware procedural shader processes said at least one graphics data argument incident to the performance of said at least one instruction without accessing the main memory of the host computing system and said hardware procedural shader outputs the result of the processing;

wherein said hardware procedural shader is a vertex shader, and said at least one instruction is an instruction with at least one floating point number argument and said vertex shader outputs the fractional portion of said at least one floating point number; and

wherein said vertex shader outputs four fractional portions of corresponding four floating point number arguments.

37. The computer system of claim 36, wherein said at least one instruction is communicated directly to said hardware procedural shader and the main memory stack of the host computing system is bypassed.

38. The computer system of claim 36, wherein incident to the processing of said at least one graphics data argument, said hardware procedural shader performs at least one of reading from and writing to on-chip register storage.

39. The computer system of claim 36, wherein said hardware procedural shader is a vertex shader, and said vertex shader further comprises a register index stored in the on-chip register storage.

40. The computer system of claim 39, wherein the register index stored in the on-chip register storage is accessed pursuant to said at least one instruction and another register is located for use in connection with carrying out said at least one instruction.

41. The computer system of claim 36, wherein said hardware procedural shader further includes a processor and an arithmetic/logic unit.

42. The computer system of claim 36, wherein said hardware procedural shader is a pixel shader, and said at least one instruction is an instruction with a plurality of floating point number arguments and said pixel shader processes the plurality of floating point number arguments to calculate a linear interpolation number representative of a linear interpolation between two of the floating point number arguments and wherein said pixel shader outputs said linear interpolation number.

43. The computer system of claim 36, wherein said hardware procedural shader is a pixel shader, and wherein said at least one instruction includes a special modifier function to be performed during processing by the pixel shader.

44. The computer system of claim 43, wherein said special modifier function performed during said processing by the pixel shader is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.