Method and apparatus for controlling current demand in an integrated circuit

• US 6,819,538 B2
• Filed: 05/15/2001
• Issued: 11/16/2004
• Est. Priority Date: 05/15/2001
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chaudhry, Rajat, Ramaraju, Ravindraraj, Zolotov, Vladimir P., Panda, Rajendran V., Blaauw, David T.
• Primary Examiner(s): Jackson, Stephen W.
• Application Number:
  US09/858,126
• Publication Number:
  US 20020171407A1
• Time in Patent Office: 1,281 Days
• Field of Search: 361/90, 361/58, 361/78, 361/100, 361/18, 361/91.1, 361/115
• US Class Current: 361/90
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations

Abstract

The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.

Claims

1. A method for controlling current demand in an integrated circuit, the integrated circuit having power consumption circuitry, the method comprising the steps of:

detecting if at least one of a predetermined overshoot and a predetermined undershoot is present or anticipated in a power supply voltage; and

if one of the predetermined overshoot or predetermined undershoot is detected in the power supply voltage, controlling current consumed by the power consumption circuitry by selectively phase shifting current in the power consumption circuitry to ensure that the power supply voltage will remain within a predetermined margin of a predetermined power supply voltage level.

2. The method of claim 1, wherein said step of detecting comprises a step of:

determining the power supply voltage directly.

3. The method of claim 1, wherein said step of detecting comprises a step of:

determining the power supply voltage by sensing at least one of power supply current, power, signal delay, and signal frequency.

4. The method of claim 1, wherein said step of detecting comprises a step of:

comparing the power supply voltage to a reference voltage.

5. The method of claim 4, wherein said step of comparing comprises steps of:

comparing the power supply voltage to a first reference voltage; and

if the power supply voltage is lower than the first reference voltage, detecting that the predetermined undershoot has occurred.

6. The method of claim 5, wherein said step of comparing further comprises steps of:

comparing the power supply voltage to a second reference voltage; and

if the power supply voltage is higher than the second reference voltage, detecting that the predetermined overshoot has occurred.

7. The method of claim 6, wherein the first reference voltage is lower than a nominal power supply voltage and the second reference voltage is higher than the nominal power supply voltage.

8. The method of claim 1, wherein the step of detecting is performed by power consumption control circuitry located on the integrated circuit.

9. The method of claim 1, wherein said step of controlling does not require use of decoupling capacitors.

10. The method of claim 1, wherein said step of controlling further comprises step of:

performing one of stopping and starting a clock provided to at least a portion of the power consumption circuitry.

11. The method of claim 1, wherein at least one parameter used in said step of controlling is user programmable.

12. The method of claim 1, wherein said step of controlling further comprises a step of adjusting a clock provided to at least a portion of the power consumption circuitry.

13. An integrated circuit, comprising:

a capacitive decoupling structure for providing current when the power supply voltage level is decreasing and for consuming current when the power supply voltage is increasing;

power consumption circuitry for consuming power; and

power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry by selectively phase shifting current in the power consumption circuitry, said power consumption control circuitry being coupled to said power consumption circuitry.

14. The integrated circuit as in claim 13, wherein said power consumption control circuitry comprises:

power consumption reduction control circuitry for reducing the current consumed by at least a portion of the power consumption circuitry; and

power consumption increase control circuitry for increasing the current consumed by at least a portion of the power consumption circuitry.

15. The integrated circuit as in claim 14, further comprising:

power dissipation circuitry, coupled to receive at least one control signal from said power consumption increase control circuitry, said power dissipation circuitry selectively dissipating power.

16. The integrated circuit as in claim 14, wherein said power consumption control circuitry further comprises:

monitoring circuitry for comparing a power supply voltage to a predetermined voltage, said monitoring circuitry being coupled to said power consumption reduction control circuitry and to said power consumption increase control circuitry.

17. The integrated circuit as in claim 14, wherein the predetermined voltage is one of a plurality of voltages, wherein the plurality of voltages comprises an upper reduction threshold voltage, a lower reduction threshold voltage, an upper increase threshold voltage, and a lower increase threshold.

18. The integrated circuit as in claim 13, further comprising:

clock adjusting circuitry, coupled to receive at least one control signal from said power consumption increase control circuitry, said clock adjusting circuitry adjusting a clock signal which is provided to at least a portion of the power consumption circuitry.

19. The integrated circuit as in claim 18, wherein said clock adjusting circuitry selectively interrupts the clock signal which is provided to the at least a portion of the power consumption circuitry.