Dielectric structure

• US 6,819,540 B2
• Filed: 10/10/2002
• Issued: 11/16/2004
• Est. Priority Date: 11/26/2001
• Status: Expired due to Fees

• Current Assignee: Shipley Company, LLC (Dow, Inc.)
• Original Assignee: Shipley Company, LLC (Dow, Inc.)
• Inventors: Jacques, David L., Rzeznik, Maria Anna, Allen, Craig S.
• Primary Examiner(s): Nguyen, Chau N.
• Assistant Examiner(s): Ha, Nguyen T.
• Application Number:
  US10/268,270
• Publication Number:
  US 20030128496A1
• Time in Patent Office: 768 Days
• Field of Search: 361/302, 361/303-305, 361/308.1, 361/311, 361/313, 361/306.1, 361/306.3, 361/321.1, 361/321.4, 361/308, 361/309, 361/310, 361/312
• US Class Current: 361/302
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0116 Porous, e.g. foam
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0212 Resin particles
• CPC Class Codes: H05K 2201/0236 Plating catalyst as filler in insulating material catalytic ink H05K2203/0709
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2203/0773 Dissolving the filler without dissolving the matrix material; Dissolving the matrix material without dissolving the filler
• CPC Class Codes: H05K 3/181 by electroless plating adhesives therefor H05K3/387
• CPC Class Codes: H05K 3/381 by special treatment of the substrate

Abstract

Dielectric structures particularly suitable for use in capacitors and having a textured surface are provided, together with methods of forming these structures. Such dielectric structures show increased adhesion of subsequently applied conductive layers.

Claims

1. A capacitor structure comprising a first conductive layer, a second conductive layer and a multilayer dielectric structure disposed between the first and second conductive layers, wherein the multilayer dielectric structure comprises a first dielectric layer and a second dielectric layer, wherein at least one of the first dielectric layer and second dielectric layer comprises pores, wherein the pores have a mean pore size of 0.5 to 1000 nm and wherein the first and second dielectric layers are selected from the group consisting of ceramics, metal oxides and combinations thereof.

2. The capacitor structure of claim 1 wherein the first dielectric layer has pores and has a thickness of <

50% of the total thickness of the dielectric structure.

3. The capacitor structure of claim 1 wherein the multilayer dielectric structure has a dielectric constant of ≦

7.

4. A printed circuit board comprising the capacitor structure of claim 1 embedded in a laminate dielectric.

5. The capacitor structure of claim 1 wherein at least one of the first dielectric layer and second dielectric layer further comprises a plating dopant.

6. A method of manufacturing a multilayer printed circuit board comprising the step of embedding the capacitor structure of claim 1 in a laminate dielectric in one or more layers of the multilayer printed circuit board.

7. A method of manufacturing the capacitor structure of claim 1 comprising disposing a first dielectric layer on a first conductive layer, disposing a second dielectric layer on the first dielectric layer, wherein at least one of the first and second dielectric layers comprises porogens, disposing a second conductive layer on the second dielectric layer, and removing the porogens to form the pores.

8. The method of claim 7 wherein the porogen is a cross-linked polymer particle.

9. The method of claim 7 further comprising the step of disposing one or more dielectric layers between the first and second dielectric layers.

10. A capacitor structure comprising a conductive substrate and a multilayer dielectric structure comprising a first dielectric layer and a second dielectric layer, wherein the second dielectric layer comprises pores, wherein the pores have a mean pore size of 0.5 to 1000 nm and wherein the first and second dielectric layers are selected from the group consisting of ceramics, metal oxides and combinations thereof.

11. A method of manufacturing a multilayer printed circuit board comprising the step of embedding the capacitor structure of claim 10 in a laminate dielectric in one or more layers of the multilayer printed circuit board.

12. A printed circuit board comprising the capacitor structure of claim 10 embedded in a laminate dielectric.

13. A method of manufacturing the capacitor structure of claim 10 comprising disposing a first dielectric layer on a conductive substrate, disposing a second dielectric layer comprising porogens on the first dielectric layer and removing the porogens to form the pores.

14. The method of claim 13 further comprising the step of disposing one or more dielectric layers between the first and second dielectric layers.

15. The method of claim 13, wherein the first and second dielectric layers are ceramics deposited by a sol-gel technique.

16. The method of claim 15 further comprising the step of annealing the first and second dielectric layers.

17. A capacitor structure comprising a conductive substrate and a multilayer dielectric structure comprising a first dielectric layer and a second dielectric layer wherein the second dielectric layer comprises pores having a mean pore size of 0.5 to 1000 nm and wherein the second dielectric layers are dried sol-gel ceramic films.

18. A capacitor structure comprising a first conductive layer, a second conductive layer and a ceramic dielectric structure disposed between the first and second conductive layers, wherein the ceramic dielectric structure has pores having a mean pore size of 0.5 to 1000 nm.