Semiconductor memory

• US 6,819,592 B2
• Filed: 03/29/2002
• Issued: 11/16/2004
• Est. Priority Date: 03/29/2001
• Status: Expired due to Term

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Goda, Akira, Noguchi, Mitsuhiro, Matsunaga, Yasuhiko
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/108,574
• Publication Number:
  US 20020159315A1
• Time in Patent Office: 963 Days
• Field of Search: 365/185.17, 365/185.12, 365/185.18, 365/185.24, 365/185.29, 365/185.28, 365/185.3, 365/185.06
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

Claims

1. A semiconductor memory including a memory cell unit, the memory cell unit comprising:

a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data;

a first select switching element electrically connecting said first terminal to a data transfer line; and

a second select switching element electrically connecting said second terminal to a reference potential line, wherein

said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and

the pass voltage applied to the control electrode of each of said unselected memory cells is made variable according to a position of said selected memory cell in said memory cell unit.

2. A semiconductor memory according to claim 1, wherein

in said data read mode, a current is carried from said data transfer line to said reference potential line through said memory cell unit, and as the number of the unselected memory cells on said data transfer line side relative to said selected memory cell increases, said pass voltage is set higher.

3. A semiconductor memory according to claim 1, wherein

in said data read mode, a current is carried from said reference potential line to said data transfer line through said memory cell unit, and as the number of the unselected memory cells on said reference potential line side relative to said selected memory cell increases, said pass voltage is set higher.

4. A semiconductor memory according to claim 1, comprising:

a pass voltage generation circuit configured to generate said pass voltage, comprising;

a booster circuit configured to generate the pass voltage higher than a power supply voltage and different according to a reference voltage or a reference current; and

a reference value generation circuit configured to generate said reference voltage or said reference current in response to address data for selecting the memory cell in said memory cell unit.

5. A semiconductor memory according to claim 4, wherein said reference value generation circuit comprises:

a logic circuit configured to input a trimming set value for adjusting the pass voltage generated in accordance with a test result and said address data, and to generate digital data corresponding to said reference voltage or said reference current; and

a circuit configured to convert output digital data of the logic circuit into an analog value, and to generate said reference voltage or said reference current.

6. A semiconductor memory according to claim 1, wherein

said semiconductor memory has a data write mode for sequentially writing the data to the memory cells from the memory cell most downstream of the read current after data of said memory cell unit is batch-erased.

7. A semiconductor memory according to claim 1, wherein

each of said memory cells has a floating gate type transistor structure having a floating gate formed on a semiconductor substrate through a tunnel insulating film, and having a control gate electrode formed on the floating gate through an insulating film.

8. A semiconductor memory according to claim 1, wherein

each of said memory cell has a MONOS type transistor structure having a layered insulating film having a tunnel insulating film, a charge accumulation layer containing nitrogen and a silicon oxide film layered on a semiconductor substrate, and having a control gate electrode formed on the layered insulating film.