Apparatus and method for a sense amplifier circuit that samples and holds a reference voltage

• US 6,819,612 B1
• Filed: 03/13/2003
• Issued: 11/16/2004
• Est. Priority Date: 03/13/2003
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Achter, Michael
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/389,149
• Time in Patent Office: 614 Days
• Field of Search: 365/185.21, 365/205, 365/207, 365/190, 365/203, 365/189.11, 365/189.08, 365/196
• US Class Current: 365/205
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A sense amplifier circuit. Specifically, a sample and hold sense amplifier circuit that is capable of sampling and holding a reference voltage comprises a reference voltage sampler circuit coupled to a cross-coupled inverter latch. The reference voltage sampler circuit is coupled to a bitline associated with a memory cell. The reference voltage is sampled from a precharge voltage taken off the bitline, and is used to read a state on a memory cell. The cross-coupled inverter latch is also coupled to the bitline, and is used for amplifying a voltage difference between an output voltage from the cross-coupled inverter latch and the reference voltage. The output voltage is based on a static bitline voltage from the bitline.

Claims

1. A sample and hold sense amplifier circuit comprising:

a reference voltage sampler circuit coupled to a bitline of a memory cell, said reference voltage sampler circuit for sampling a reference voltage from a precharge voltage of said bitline, said reference voltage for reading a state on a memory cell;

a cross-coupled inverter latch coupled to said reference voltage sampler circuit and coupled to said bitline, said cross-coupled inverter latch for amplifying a voltage difference between an output voltage of said cross-coupled inverter latch and said reference voltage, said output voltage being based on a static bitline voltage from said bitline.

2. The sample and hold sense amplifier of claim 1, further comprising:

a precharge transistor circuit coupled to said cross-coupled inverter latch, said precharge transistor circuit for achieving a stable state in said cross-coupled inverter latch during a precharging cycle in which said reference voltage is sampled; and

a sensing circuit coupled to said cross-coupled inverter latch to enable said cross-coupled inverter latch to amplify said voltage difference after said precharging cycle.

3. The sample and hold sense amplifier of claim 2, wherein in said stable state said reference voltage is equal to said output voltage of said cross-coupled inverter latch.

4. The sample and hold sense amplifier of claim 2, wherein said reference voltage during said stable state is approximately equal to said bitline precharge voltage.

5. The sample and hold sense amplifier of claim 1, wherein said precharge transistor circuit further comprises:

a precharge pulling circuit coupled to said cross-coupled inverter latch, said precharge pulling circuit for disabling said cross-coupled inverter latch when sampling said reference voltage, and for enabling said cross-coupled inverter latch when amplifying said voltage difference.

6. The sample and hold sense amplifier of claim 5, wherein said precharge pulling circuit further comprises:

a precharge pull up circuit coupled to a first node in said cross-coupled inverter latch, said precharge pull up circuit for disabling a first inverter amplifier in said cross-coupled inverter latch when sampling said reference voltage by pulling said first node low; and

a precharge pull down circuit coupled to a second node in said cross-coupled inverter latch, said precharge pull down circuit for disabling a second inverter amplifier in said cross-coupled inverter latch when sampling said reference voltage by pulling said second node high.

7. The sample and hold sense amplifier of claim 6 further comprising:

a pull up circuit coupled to said first node, said pull up circuit for enabling said first inverter amplifier when amplifying said voltage difference by pulling said first node high; and

a pull down circuit coupled to said second node, said pull down circuit for enabling said second inverter amplifier when amplifying said voltage difference by pulling said second node low.

8. The sample and hold sense amplifier of claim 1, further comprising:

a sensing circuit coupled to said cross-coupled inverter latch, said sensing circuit for swinging to a high voltage the greater of said bitline voltage and said reference voltage through said cross-coupled inverter latch, and swinging to a low voltage the lesser of said bitline voltage and said reference voltage through said cross-coupled inverter latch to amplify said voltage difference.

9. The sample and hold sense amplifier of claim 8, wherein said high voltage is a supply voltage to said cross-coupled inverter latch, and said low voltage is ground.

10. A sample and hold sense amplifier circuit comprising:

a first pass gate transistor coupled to a bitline of a memory cell for passing voltage from said bitline, said first pass gate transistor controlled by a first precharge signal;

a second pass gate transistor coupled to said bitline for passing said voltage from said bitline, said second pass gate transistor controlled by a second precharge signal;

a reference voltage sampler circuit coupled to said first pass gate transistor, said reference voltage sampler for sampling and holding a reference voltage determined from a precharge voltage of said bitline; and

a cross-coupled inverter latch coupled to said first pass gate transistor and said second pass gate transistor, said cross-coupled inverter latch for amplifying a voltage difference between an output voltage of said cross-coupled inverter latch and said reference voltage, said output voltage based on a static bitline voltage from said bitline.

11. The sample and hold sense amplifier circuit of claim 10, further comprising:

a plurality of capacitive elements for holding said reference voltage when amplifying said voltage difference.

12. The sample and hold sense amplifier circuit of claim 10, further comprising:

a precharge transistor circuit coupled to said cross-coupled inverter latch, said precharge transistor circuit for achieving a stable state in said cross-coupled inverter latch during a precharging cycle in which said reference voltage is sampled; and

a sensing circuit coupled to said cross-coupled inverter latch for enabling said cross-coupled inverter latch to amplify said voltage difference after said precharging cycle.

13. The sample and hold sense amplifier circuit of claim 12, wherein said reference voltage during said stable state is approximately equal to said bitline precharge voltage.

14. The sample and hold sense amplifier circuit of claim 10, wherein said precharge transistor circuit further comprises:

a precharge pull up circuit coupled to a node in said cross-coupled inverter latch, said precharge pull up circuit for disabling a first inverter amplifier in said cross-coupled inverter latch when sampling said reference voltage by pulling said node low, and for enabling said first inverter amplifier when amplifying said voltage difference by pulling said node high.

15. The sample and hold sense amplifier circuit of claim 10, wherein said precharge transistor circuit further comprises:

a precharge pull down circuit coupled to a node in said cross-coupled inverter latch, said precharge pull down circuit for disabling a second inverter amplifier in said cross-coupled inverter latch when sampling said reference voltage by pulling said node high, and for enabling said second inverter amplifier when amplifying said voltage difference by pulling said node low.

16. The sample and hold sense amplifier circuit of claim 10, further comprising:

a shorting circuit coupled to said cross-coupled inverter latch, said shorting circuit for equalizing said reference voltage and said output voltage when said reference voltage is sampled.

17. The sample and hold sense amplifier circuit of claim 10, wherein said second pass gate transistor inhibits current flow back to said bitline when amplifying said voltage difference.

18. The sample and hold sense amplifier circuit of claim 10, further comprising:

a current supply coupled to said bitline compensating for leakage current in said bitline.

19. A method for sampling and holding a reference voltage in a sensing circuit comprising:

a) sampling said reference voltage based on a precharge voltage of a bitline during a precharge cycle, said reference voltage equal to a precharge voltage of said bitline;

b) disabling a cross-coupled inverter latch during said precharge cycle, said cross-coupled inverter latch coupled to said bitline;

c) holding said reference voltage after said precharge cycle;

d) amplifying a voltage difference between an output voltage of said cross-coupled inverter latch and said reference voltage by enabling said cross-coupled inverter latch after said precharge cycle, said output voltage being based on a static bitline voltage from said bitline.

20. The method as described in claim 19, further comprising:

before a), precharging said bitline to said precharge voltage during said precharge cycle.

21. The method as described in claim 19, wherein b) further comprises:

b1) reaching a stable state in said cross-coupled inverter latch during said precharging cycle, such that, said reference voltage is equal to a precharged output voltage of said cross-coupled inverter latch, said precharged voltage being based on a precharged voltage from said bitline.

22. The method as described in claim 19, wherein b) further comprises:

b1) pulling down a latch pull up node in said cross-coupled inverter latch to disable a first inverter amplifier in said cross-coupled inverter latch; and

b2) pulling up a latch pull down node in said cross-coupled inverter latch to disable a second inverter amplifier in said cross-coupled inverter latch, said second inverter amplifier coupled to said first inverter amplifier.

23. The method as described in claim 19, wherein c) further comprises:

c1) using capacitive elements to hold said reference voltage.

24. The method as described in claim 19, wherein d) further comprises:

d1) swinging to a high voltage the greater of said output voltage and said reference voltage through said cross-coupled inverter latch; and

d2) swinging to a low voltage the lesser of said output voltage and said reference voltage through said cross-coupled inverter latch to amplify said voltage difference.

25. The method as described in claim 22, wherein d) further comprises:

d1) pulling up said latch pull up node to enable said cross-coupled inverter latch; and

d2) pulling down said latch pull down node to enable said cross-coupled inverter latch.

26. The method as described in claim 19, further comprising:

compensating for leakage current from said memory cell by adding current to current from said bitline.