Memory control device and LSI

• US 6,820,152 B2
• Filed: 04/10/2002
• Issued: 11/16/2004
• Est. Priority Date: 04/25/2001
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kanzaki, Hideyuki, Osaka, Masataka
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US10/120,327
• Publication Number:
  US 20020161956A1
• Time in Patent Office: 951 Days
• Field of Search: 710/113-125, 710/240-244
• US Class Current: 710/244
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.

Claims

1. A memory control device for arbitrating memory access contention among a plurality of bus masters sharing a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, the memory control device comprising:

holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate information indicating (i) a transfer rate at which a corresponding bus master performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;

reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;

bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a bus master takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding bus master is capable of transferring at a corresponding transfer rate within the reference time period; and

use right granting means for granting the bus use right to each bus master for a corresponding bus use permission time period within each reference time period that repeats cyclically.

2. The memory control device of claim 1, comprising

detecting means for detecting a bus request from each bus master, wherein

the use right granting means grants the bus use right for a current reference time period to each bus master of which a bus request has been detected by the detecting means prior to a start of the current reference time period.

3. The memory control device of claim 2, wherein

the bus masters are classified into (i) regular type bus masters, each of which is required to perform data transfer to or from the memory at a fixed transfer rate, and (ii) irregular type bus masters, which are bus masters other than the regular type bus masters,

the holding means holds the transfer rate information regarding each regular type bus master,

the bus use permission time period calculating means calculates the bus use permission time periods for each regular type bus master, and

the use right granting means grants the bus use right for each reference time period (i) to each regular type bus master of which a bus request has been detected prior to a start of the current reference time period, the bus use right being granted for a corresponding bus use permission time period, and (ii) to each irregular type bus master for, at the maximum, a time period remaining after subtracting from the reference time period a total amount of the bus use permission time periods calculated for each of the regular type bus masters of which bus requests have been detected.

4. The memory control device of claim 3, wherein

the use right granting means grants the bus use right for each reference time period to an irregular type bus master immediately after terminating the bus use right granted to a regular type bus master when the detecting means detects a bus request from the irregular type bus master during the time the bus use right is being granted to the regular type bus master.

5. The memory control device of claim 4, wherein

the holding means acquires the transfer rate information from a source external to the memory control device, and holds the acquired transfer rate information.

6. The memory control device of claim 4, wherein

the holding means holds the transfer rate information within the memory control device in a memory area that is rewritable by an external device.

7. The memory control device of claim 4, wherein

the memory control device is connected to each bus master through a signal line used for granting the bus use right, and

the use right granting means grants the bus use right to each bus master by putting a signal line connected to the bus master into an active state for a corresponding bus use permission time period.

8. The memory control device of claim 1, wherein

the reference time period calculating means determines, as the reference time period, the shortest ensuring time period among all the ensuring time periods.

9. The memory control device of claim 1, wherein

the holding means acquires the transfer rate information from a source external to the memory control device, and holds the acquired transfer rate information.

10. A memory control device for arbitrating memory access contention among a plurality of bus masters accessing separate memory areas within a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, the memory control device comprising:

holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate information indicating (i) a transfer rate at which a corresponding bus master performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;

reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;

bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a bus master takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding bus master is capable of transferring at a corresponding transfer rate within the reference time period; and

use right granting means for granting the bus use right to each bus master for a corresponding bus use permission time period within each reference time period that repeats cyclically.

11. The memory control device of claim 10, wherein

detecting means for detecting a bus request from each bus master, wherein

the use right granting means grants the bus use right for a current reference time period to each bus master of which a bus request has been detected by the detecting means prior to a start of the current reference time period.

12. The memory control device of claim 11, wherein

the bus masters are classified into (i) regular type bus masters, each of which is required to perform data transfer to or from the memory at a fixed transfer rate, and (ii) irregular type bus masters, which are bus masters other than the regular type bus masters,

the holding means holds the transfer rate information regarding each regular type bus master,

the bus use permission time period calculating means calculates the bus use permission time periods for each regular type bus master, and

the use right granting means grants the bus use right for each reference time period (i) to each regular type bus master of which a bus request has been detected prior to a start of the current reference time period, the bus use right being granted for a corresponding bus use permission time period, and (ii) to each irregular type bus master for, at the maximum, a time period remaining after subtracting from the reference time period a total amount of the bus use permission time periods calculated for each of the regular type bus masters of which bus requests have been detected.

13. The memory control device of claim 12, wherein

the use right granting means grants the bus use right for each reference time period to an irregular type bus master immediately after terminating the bus use right granted to a regular type bus master when the detecting means detects a bus request from the irregular type bus master during the time the bus use right is being granted to the regular type bus master.

14. An LSI including (i) a plurality of circuits that share a memory and (ii) a memory control device for arbitrating memory access contention by selectively granting a bus use right that permits the usage a memory bus to one of the plurality of circuits at a time, each circuit is required to perform data transfer to or from the memory at a fixed transfer rate, the memory control device comprising:

holding means for holding transfer rate information regarding each of the plurality of the circuits, the transfer rate information indicating (i) a transfer rate at which a corresponding circuit performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;

reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;

bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a circuit takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding circuit is capable of transferring at a corresponding transfer rate within the reference time period; and

use right granting means for granting the bus use right to each circuit for a corresponding bus use permission time period within each reference time period that repeats cyclically.

15. The LSI of claim 14, wherein

each circuit performs data transfer to or from one of separate memory areas within the memory.

16. The LSI of claim 14, wherein

the memory control device comprises

detecting means for detecting a bus request from each circuit, wherein

the use right granting means grants the bus use right for a current reference time period to each circuit of which a bus request has been detected by the detecting means prior to a start of the current reference time period.

17. The LSI of claim 16, wherein

the circuits are classified into (i) regular type bus masters, each of which is required to perform data transfer to or from the memory at a fixed transfer rate, and (ii) irregular type bus masters, which are circuits other than the regular type bus masters,

the holding means holds the transfer rate information regarding each regular type bus master,

the bus use permission time period calculating means calculates the bus use permission time periods for each regular type bus master, and

the use right granting means grants the bus use right for each reference time period (i) to each regular type bus master of which a bus request has been detected prior to a start of the current reference time period, the bus use right being granted for a corresponding bus use permission time period, and (ii) to each irregular type bus master for, at the maximum, a time period remaining after subtracting from the reference time period a total amount of the bus use permission time periods calculated for each of the regular type bus masters of which bus requests have been detected.

18. The LSI of claim 17, wherein

the use right granting means grants the bus use right for each reference time period to an irregular type bus master immediately after terminating the bus use right granted to a regular type bus master when the detecting means detects a bus request from the irregular type bus master during the time the bus use right is being granted to the regular type bus master.

19. The LSI of claim 14, wherein

the holding means acquires the transfer rate information from a source external to the memory control device, and holds the acquired transfer rate information.