Skew calibration means and a method of skew calibration

• US 6,820,234 B2
• Filed: 10/01/2001
• Issued: 11/16/2004
• Est. Priority Date: 06/29/1998
• Status: Expired due to Term

• Current Assignee: Computer Circuit Operations LLC
• Original Assignee: Acuid Corp. Ltd.
• Inventors: Abrossimov, Igor Anatolievich, Klotchkov, Ilya Valerievich, Deas, Alexander Roger, Atyunin, Vasily Grigorievich
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US09/967,535
• Publication Number:
  US 20030208717A1
• Time in Patent Office: 1,142 Days
• Field of Search: 714/700, 714/814, 714/815, 714/816, 714/811, 714/798, 713/400, 713/401, 713/500, 713/503, 713/600
• US Class Current: 714/814
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register'"'"'s timing within each plurality. The apparatus preferably further comprises a storage means for recording and storing information on skew in a communication media, for at least one data pattern transmitted through the transmission line and a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above skew.

Claims

1. An apparatus for high speed communication, comprising:

a plurality of driving registers, each driving register having a plurality of inputs and outputs, at least one output of each said driving register connectable to at least one communication line, said driving registers latching transmitted signals;

a plurality of receiving registers, each receiving register having a plurality of inputs and outputs, at least one input of each said receiving register connectable to at least one said communication line, said receiving registers latching received signals;

a main clock for generating a main clock signal;

a reference clock for generating a reference signal for calibrating the receiving registers;

said reference clock being associated with said main clock;

a first set of phase shift means associated with said plurality of driving registers, for the relative alignment of the driving registers'"'"' timing within the plurality of driving registers.

2. The apparatus according to claim 1, further comprising a common transmission line of known signal propagation rate for supplying the said reference signal.

3. The apparatus according to claim 2, wherein each of said receiving registers is connected to said reference clock by said common transmission line of known signal propagation rate.

4. The apparatus according to claim 1, wherein each of said phase shift means is pre-calibrated by varying a calibration frequency.

5. The apparatus according to claim 1, wherein said phase shift means comprises at least one of:

a variable delay, a programmable delay, an analogue vernier, a digital vernier.

6. The apparatus according to claim 1, wherein each of said receiving registers for latching signals received from said communication line is pre-calibrated by determining a minimal feasible time delay between the reference clock edge and a moment when the register latches data.

7. The apparatus according to claim 1, further comprising a second set of phase shift means associated with said plurality of receiving registers, for relative alignment of the receiving register'"'"'s timing within said plurality of receiving registers.

8. The apparatus according to claim 1, further comprising a storage means for recording and storing information on skew in a communication media, for at least one data pattern transmitted through the communication line.

9. The apparatus according to claim 8, further comprising a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above skew.

10. The apparatus according to claim 1, further comprising a third set of phase shift means associated with said pluralities of driving and receiving registers, for relative alignment of the register'"'"'s timing between said pluralities of driving and receiving registers, said pluralities of registers being connected to the main clock via said third set of phase shift means.

11. The apparatus according to claim 10, wherein said third plurality of phase shift means comprises at least one shift means associated with each of the said pluralities of driving and receiving registers.

12. The apparatus according to claim 1, wherein the driving registers and receiving registers are interconnected so that outputs of driving registers are connected via respective communication lines to the inputs of respective receiving registers to calibrate said plurality of driving registers.

13. A method for reducing timing uncertainty of a communication apparatus, comprising:

calibrating a plurality of receiving registers of the communication apparatus using at least one set of programmable delays, each of said receiving registers being connectable to at least one communication line, in relation to a reference clock edge;

calibrating a propagation delay of a plurality of driving registers of the communication apparatus, each of said driving registers being connectable to said at least one communication line, using the calibrated receiving registers; and

performing relative alignment of the programmable delays to a main clock edge.

14. The method according to claim 13, further comprising calibrating a respective programmable delay for each receiving register before calibrating the receiving registers.

15. The method according to claim 14, wherein the programmable delays are pre-calibrated by varying a calibration frequency and fixing the difference in time of the two transition moments.

16. The method according to claim 13, wherein the accuracy of at least one of calibration of the receiving registers and calibration of the driving registers is increased by determining for at least one of the receiving and driving registers, a minimal feasible time delay between the reference clock edge and a moment when at least one of the receiving and driving registers latches data.

17. The method according to claim 16, wherein the determination for minimal feasible time delay is performed twice, once for the falling edge of said reference clock, and again for the rising edge of said reference clock.

18. A method according to claim 13, wherein the propagation delay of each of the driving registers is calibrated by varying delays to best match an output transition with a latch time of at least one of said receiving registers.

19. The method according to claim 13, wherein the propagation delays are calibrated for each individual bit of the receiving register data.

20. The method according to claim 13, further comprising transmitting of data through the communication line provided by at least one driver and measuring a skew for at least one data pattern transmitted through the communication line.

21. The method according to claim 13, further comprising recording and storing information on skew in said at least one communication line, for at least one data pattern transmitted through the communication line.

22. The method according to claim 21, further comprising generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the stored skew information, so as to compensate the above skew of the communication line.

23. The method according to claim 22, wherein the information is stored on skew caused by inter-symbol interference in the transmission media.

24. The method according to claim 22, wherein the information is stored on skew caused by cross-talk influence in the transmission media.

25. The method according to claim 13, wherein said receiving registers are calibrated with reference to a periodic reference clock edge.

26. The method according to claim 13, wherein at least one of the calibration of the receiving registers and the calibration of the driving registers is partially or completely computer implemented.

27. A computer readable medium including a computer readable program means for implementing or simulating hardware functions of a communication apparatus comprising:

a plurality of driving registers connectable to at least one communication line, said driving registers latching transmitted signals;

a plurality of receiving registers connectable to said at least one communication line for latching signals received from said communication line;

a main clock for generating a main clock signal;

a reference clock for generating reference signals for calibrating the receiving registers;

said reference clock being associated with said main clock;

a first set of phase shift means associated with said plurality of driving registers, for the relative alignment of the driving registers'"'"' timing.

28. A timing uncertainty reduction system for calibration of a high speed communication apparatus, comprising:

at least one driving register for latching transmitted signals, each said driving register having a plurality of inputs and outputs;

at least one receiving register for latching received signals, each said receiving register having a plurality of inputs and outputs;

a main clock for generating a main clock signal;

a reference clock for generating a reference signal for calibrating the receiving register or registers;

said reference clock being associated with said main clock; and

a first set of phase shift means associated with said driving register or registers, for the relative alignment of the driving signals'"'"' timing.

29. The system according to claim 28, further comprising a storage means connected to said at least one driving register or at least one receiving register for recording and storing information on timing uncertainty in a communication media, for at least one data pattern transmitted through the communication media.

30. The system according to claim 29, further comprising a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above timing uncertainty.

31. The system according to claim 29, wherein the information on timing uncertainty is stored on skew caused by inter-symbol interference in the communication media.

32. The system according to claim 29, wherein the information on timing uncertainty is stored on skew caused by cross-talk influence in the communication media.

33. The system according to claim 30, wherein the correction is applied using said first set of phase shift means.

34. The system according to claim 30, wherein the correction is applied using a second set of phase shift means associated with said plurality of receiving registers, for relative alignment of the receiving register'"'"'s timing within said plurality of receiving registers.

35. The system according to claim 28, further comprising a common transmission line of known signal propagation rate for supplying the said reference signal.

36. The system according to claim 28, wherein each of said receiving registers is connected to said reference clock by said common transmission line of known signal propagation rate.

37. The system according to claim 28, wherein each of said phase shift means is pre-calibrated by varying a calibration frequency.

38. The system according to claim 28, wherein each of said receiving registers for latching signals is pre-calibrated by determining a minimal feasible time delay between the reference clock edge and a moment when the register latches data.

39. A computer program product for implementing a method of reducing timing uncertainty of a communication apparatus, said computer program product comprising

a computer usable medium having computer readable program code means embodied thereon, said computer program code means comprising

a computer readable program code means for causing a computer to perform transmitting of data through at least one communication line provided by at least one driver and measuring a skew for at least one data pattern transmitted through the communication line;

a computer readable program code means for causing a computer to perform recording and storing information on skew in said at least one communication line, for at least one data pattern transmitted through the communication line;

a computer readable program code means for causing a computer to perform generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the skew information of the communication line, so as to compensate the above skew;

a computer readable program code means for causing a computer to perform calibration of a plurality of receiving registers of the communication apparatus using at least one set of programmable delays, each of said receiving registers being connectable to said at least one communication line, in relation to a reference clock edge;

a computer readable program code means for causing a computer to perform calibrating a propagation delay of a plurality of driving registers of the communication apparatus, each of said driving registers being connectable to said at least one communication line, using the calibrated receiving registers; and

a computer readable program code means for causing a computer to perform relative alignment of the programmable delays to a main clock edge.