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Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

  • US 6,821,826 B1
  • Filed: 09/30/2003
  • Issued: 11/23/2004
  • Est. Priority Date: 09/30/2003
  • Status: Active Grant
First Claim
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1. A three-dimensional (3D) integration scheme comprising:

  • providing a first interconnect structure comprising at least a first semiconductor device located on a surface of a first Si-containing layer of a first silicon-on-insulator substrate, said first Si-containing layer having a first surface orientation that is optimal for said first semiconductor device;

    attaching a handling wafer to a surface of the first interconnect structure;

    providing a second interconnect structure comprising at least a second semiconductor device that differs from the first semiconductor device on a surface of a second Si-containing layer of a second silicon-on-insulator substrate, said second Si-containing layer having a second surface orientation that is optimal for said second semiconductor device;

    bonding the first and second interconnect structures to each other; and

    removing the handling wafer.

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