Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
First Claim
1. A three-dimensional (3D) integration scheme comprising:
- providing a first interconnect structure comprising at least a first semiconductor device located on a surface of a first Si-containing layer of a first silicon-on-insulator substrate, said first Si-containing layer having a first surface orientation that is optimal for said first semiconductor device;
attaching a handling wafer to a surface of the first interconnect structure;
providing a second interconnect structure comprising at least a second semiconductor device that differs from the first semiconductor device on a surface of a second Si-containing layer of a second silicon-on-insulator substrate, said second Si-containing layer having a second surface orientation that is optimal for said second semiconductor device;
bonding the first and second interconnect structures to each other; and
removing the handling wafer.
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Abstract
Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.
322 Citations
19 Claims
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1. A three-dimensional (3D) integration scheme comprising:
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providing a first interconnect structure comprising at least a first semiconductor device located on a surface of a first Si-containing layer of a first silicon-on-insulator substrate, said first Si-containing layer having a first surface orientation that is optimal for said first semiconductor device;
attaching a handling wafer to a surface of the first interconnect structure;
providing a second interconnect structure comprising at least a second semiconductor device that differs from the first semiconductor device on a surface of a second Si-containing layer of a second silicon-on-insulator substrate, said second Si-containing layer having a second surface orientation that is optimal for said second semiconductor device;
bonding the first and second interconnect structures to each other; and
removing the handling wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A 3D integration scheme of the present invention comprising:
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bonding a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation to a surface of a pre-fabricating wafer having at least one second semiconductor device on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and
forming at least one first semiconductor device is said first SOI layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification