Display apparatus with improved sensing speed of resolution change and sensing method thereof

• US 6,822,660 B2
• Filed: 07/30/2001
• Issued: 11/23/2004
• Est. Priority Date: 04/06/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Su
• Primary Examiner(s): Eisen, Alexander
• Application Number:
  US09/918,254
• Publication Number:
  US 20020145597A1
• Time in Patent Office: 1,212 Days
• Field of Search: 345/3--, 345/98-100, 345/204, 345/698, 345/699, 345/211-213, 348/558, 348/556, 348/553, 348/521, 348/524, 348/500, 348/510, 348/513, 348/525, 348/526
• US Class Current: 345/699
• CPC Class Codes: G09G 1/167 Details of the interface to the display terminal specific for a CRT details suitable for both CRT and flat panel G09G5/006, specific for a flat panel G09G3/2096

Abstract

A display apparatus is provided for displaying a picture signal which is synchronized with a synchronization signal provided from a host. The display apparatus includes: a counting circuit for counting a first number of pulses of the synchronization signal provided from the host, and generating a counted number of pulses in a predetermined time period; a register for storing the first number of the pulses provided from the counting circuit; and a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different.

Claims

1. A display apparatus for displaying a picture signal synchronized with a synchronization signal provided from a host, the display apparatus comprising:

a counting circuit for counting a first number of pulses of the synchronization signal provided from the host, and generating a counted number of pulses in a predetermined time period;

a register for storing the first number of the pulses provided from the counting circuit; and

a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different,

wherein the counting circuit comprises a counter for counting the number of pulses of the synchronization signal and the counter is reset by a control signal from the comparator, and

wherein the synchronization signal is a horizontal synchronization signal.

2. The display apparatus of claim 1, wherein the counting circuit further comprises:

a timer for generating a control signal every predetermined time period; and

a switching circuit transferring the counted number of pulses to an output in response to the control signal generated by the timer.

3. The display apparatus of claim 2, wherein the timer generates the control signal every 1 millisecond.

4. A display apparatus for displaying a picture signal synchronized with a composite signal of a host horizontal synchronization signal and a host vertical synchronization signal, the display apparatus comprising:

a synchronization signal separator for dividing the composite signal into a horizontal synchronization signal and a vertical synchronization signal;

a counting circuit for counting a first number of pulses of the horizontal synchronization signal outputted from the synchronization signal separator, and generating a counted number of pulses every predetermined time period;

a register for storing the first number of pulses provided from the counting circuit; and

a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different,

wherein the counting circuit comprises a counter for counting the number of pulses of the horizontal synchronization signal outputted from the synchronization signal separator and the counter is reset by a control signal provided from the comparator.

5. The display apparatus of claim 4, wherein the horizontal synchronization signal outputted from the synchronization signal separator is the same as the composite signal.

6. The display apparatus of claim 4, further comprising a flag register, wherein, when the vertical synchronization signal outputted from the synchronization signal separator is activated, the flag register is set and the comparator determines whether a difference between the first number of pulses and the second number of pulses is due to a resolution change or a frequency change in the composite signal resulting from activation of the host vertical synchronization signal.

7. The display apparatus of claim 4, wherein the synchronization signal separator comprises an up/down counter performing an up-count when the composite signal is a first level, and performing a down-count when the composite signal is a second level, and an overflow signal provided from the up/down counter is the vertical synchronization signal.

8. The display apparatus of claim 4, wherein the counter generates the counted number of pulses and the counting circuit further comprises:

a timer generating a control signal in a predetermined time period; and

a switching circuit transferring the counted number of pulses from the counter to an output in response to the control signal.

9. The display apparatus of claim 8, wherein the timer generates the control signal every 1 millisecond.

10. A display apparatus having an embedded micro controller, the micro controller comprising:

a counting circuit for counting a first number of pulses of the synchronization signal provided from a host, and generating a counted number of pulses in a predetermined time period;

a register for storing the first number of the pulses provided from the counting circuit;

a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different,

wherein the counting circuit comprises a counter for counting the number of pulses of the synchronization signal from the host and for generating the counted number of pulses, and wherein the counter is reset by a control signal from the comparator, and

a flag register set by an overflow signal of the synchronization signal, wherein the comparator does not compare the second number of pulses with the first number of pulses when the flag register is set.

13. The micro controller of claim 10, wherein the resolution change sensing signal serves as a signal for a video mute in the display apparatus.

11. The micro controller of claim wherein the counting circuit further comprises:

a timer generating a control signal in a predetermined time period; and

a switching circuit transferring the counted number of pulses to an output in response to the control signal generated by the timer.

12. The micro controller of claim 11, wherein the timer generates the control signal every 1 millisecond.

14. A method for sensing resolution change in a display apparatus displaying a picture signal synchronized with a synchronization signal provided from a host, the method comprising the steps of:

generating a first counted number of pulses in a first predetermined time period by counting a first number of pulses of the synchronization signal from the host;

generating a second counted number of pulses in a second predetermined time period by counting a second number of pulses of the synchronization signal from the host;

comparing the first counted number of pulses and the second counted number of pulses;

generating a resolution change sensing signal when the first counted number of pulses and the second counted number of pulses are different and the difference between the first counted number of pulses and the second counted number of pulses is not due to a frequency change caused by activation of a component of the synchronization signal; and

generating a reset signal when the first counted number of pulses and the second counted number of pulses are the same.

15. The method of claim 14, the first counted number of pulses and the second counted number of pulses are generated every 1 millisecond.

16. A display apparatus for displaying a picture signal synchronized with a composite signal of a host horizontal synchronization signal and a host vertical synchronization signal, the display apparatus comprising:

a synchronization signal separator for dividing the composite signal into a horizontal synchronization signal and a vertical synchronization signal;

a counting circuit for counting a first number of pulses of the horizontal synchronization signal outputted from the synchronization signal separator, and generating a counted number of pulses every predetermined time period;

a register for storing the first number of pulses provided from the counting circuit;

a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different; and

a flag register, wherein, when the vertical synchronization signal outputted from the synchronization signal separator is activated, the flag register is set and the comparator determines whether a difference between the first number of pulses and the second number of pulses is due to a resolution change or a frequency change in the composite signal resulting from activation of the host vertical synchronization signal.

17. A display apparatus for displaying a picture signal synchronized with a composite signal of a host horizontal synchronization signal and a host vertical synchronization signal, the display apparatus comprising:

a synchronization signal separator for dividing the composite signal into a horizontal synchronization signal and a vertical synchronization signal;

a counting circuit for counting a first number of pulses of the horizontal synchronization signal outputted from the synchronization signal separator, and generating a counted number of pulses every predetermined time period;

a register for storing the first number of pulses provided from the counting circuit; and

a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different,

wherein the horizontal synchronization signal outputted from the synchronization signal separator is the same as the composite signal.

18. A display apparatus for displaying a picture signal synchronized with a composite signal of a host horizontal synchronization signal and a host vertical synchronization signal, the display apparatus comprising:

a synchronization signal separator for dividing the composite signal into a horizontal synchronization signal and a vertical synchronization signal;

a counting circuit for counting a first number of pulses of the horizontal synchronization signal outputted from the synchronization signal separator, and generating a counted number of pulses every predetermined time period;

a register for storing the first number of pulses provided from the counting circuit;

a comparator for comparing a second number of pulses newly provided from the counting circuit with the first number of pulses stored in the register, and generating a resolution change sensing signal when the first number of pulses and the second number of pulses are different; and

a flag register, wherein, when the vertical synchronization signal outputted from the synchronization signal separator is activated, the flag register is set and the comparator does not compare the second number of pulses with the first number of pulses.