Dual stage communication processor
First Claim
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1. An apparatus for receiving a data transmission signal operating at a predetermined transmission rate and generating an improved data transmission signal, said apparatus comprising:
- a decoding mechanism configured to receive said data transmission signal and a clock reference signal having a predetermined clock rate matching said predetermined transmission rate of said data transmission signal, said decoding mechanism being configured to compensate for amplitude and phase distortions of said data transmission signal and produce a corrected data signal, to split said corrected data signal into component data signals, to generate a data clock reference signal based on said data transmission signal and said clock reference signal, and to convert said component data signals into digital component data signals synchronized to said data clock reference signal;
a first coupler and impedance matching mechanism configured to couple said data transmission signal to said decoding mechanism, said first coupler and impedance matching mechanism including a transformer having primary and secondary windings isolated from a ground connection, a resistive element matching the impedance of a transmission facility conveying said data transmission signal, and a high frequency coupling mechanism for filtering said coupled data transmission signal;
an encoding mechanism coupled to said decoding mechanism, said encoding mechanism configured to receive said digital component data signals and said data clock reference signal and to convert said digital component data signals into analog component data signals, wherein said decoding mechanism comprises;
an attenuating mechanism coupled to said first coupler and impedance matching mechanism, said attenuating mechanism configured to initially adjust the amplitude of said coupled data transmission signal to a predetermined level, a gain and equalizing mechanism coupled to said attenuating mechanism, said gain and equalizing mechanism configured to adjust the gain and compensate for amplitude and phase distortions of said coupled data transmission signal, a signal splitting mechanism to split the corrected data transmission signal into component data signals, a slicing mechanism coupled to said gain and equalizing mechanism and said signal splitting mechanism, said slicing mechanism configured to convert said component data signals into digital component data signals, a combiner mechanism coupled to said slicing mechanism, said combiner mechanism configured to combine said digital component data signals into a composite digital data signal, and a phase lock loop mechanism configured to receive said composite digital data signal, lock into a frequency and phase of said composite digital data signal, and generate said data clock reference signal, said phase lock loop mechanism including a phase detector to detect the phase of said composite digital data signal, a loop filter to filter out high frequency noise components of said composite digital signal, and a voltage controlled oscillator for generating said frequency and phase information from said composite digital signal, and wherein said apparatus outputs at least one of said analog component data signals as the improved data transmission signal.
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Abstract
A communications processor is presented that is capable of receiving a potentially degraded data transmission signals operating at high transmission rates and generating an improved data transmission signal in a manner that allows the signals to be transmitted over longer distances than is otherwise possible using conventional methods. The communications processor includes a decoding mechanism configured to compensate for amplitude and phase distortions of the data transmission signal, to split the corrected data signal into component data signals, to generate a data clock reference signal based on the data transmission signal and the external clock reference signal, and to convert the component data signals into digital component data signals synchronized to the data clock reference signal. The communications processor further includes an encoding mechanism configured to receive the digital component data signals and the data clock reference signal and to convert the digital component data signals into analog component data signals. The communications processor then selectively outputs at least one of the analog component data signals as the improved data transmission signal.
79 Citations
20 Claims
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1. An apparatus for receiving a data transmission signal operating at a predetermined transmission rate and generating an improved data transmission signal, said apparatus comprising:
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a decoding mechanism configured to receive said data transmission signal and a clock reference signal having a predetermined clock rate matching said predetermined transmission rate of said data transmission signal, said decoding mechanism being configured to compensate for amplitude and phase distortions of said data transmission signal and produce a corrected data signal, to split said corrected data signal into component data signals, to generate a data clock reference signal based on said data transmission signal and said clock reference signal, and to convert said component data signals into digital component data signals synchronized to said data clock reference signal;
a first coupler and impedance matching mechanism configured to couple said data transmission signal to said decoding mechanism, said first coupler and impedance matching mechanism including a transformer having primary and secondary windings isolated from a ground connection, a resistive element matching the impedance of a transmission facility conveying said data transmission signal, and a high frequency coupling mechanism for filtering said coupled data transmission signal;
an encoding mechanism coupled to said decoding mechanism, said encoding mechanism configured to receive said digital component data signals and said data clock reference signal and to convert said digital component data signals into analog component data signals, wherein said decoding mechanism comprises;
an attenuating mechanism coupled to said first coupler and impedance matching mechanism, said attenuating mechanism configured to initially adjust the amplitude of said coupled data transmission signal to a predetermined level, a gain and equalizing mechanism coupled to said attenuating mechanism, said gain and equalizing mechanism configured to adjust the gain and compensate for amplitude and phase distortions of said coupled data transmission signal, a signal splitting mechanism to split the corrected data transmission signal into component data signals, a slicing mechanism coupled to said gain and equalizing mechanism and said signal splitting mechanism, said slicing mechanism configured to convert said component data signals into digital component data signals, a combiner mechanism coupled to said slicing mechanism, said combiner mechanism configured to combine said digital component data signals into a composite digital data signal, and a phase lock loop mechanism configured to receive said composite digital data signal, lock into a frequency and phase of said composite digital data signal, and generate said data clock reference signal, said phase lock loop mechanism including a phase detector to detect the phase of said composite digital data signal, a loop filter to filter out high frequency noise components of said composite digital signal, and a voltage controlled oscillator for generating said frequency and phase information from said composite digital signal, and wherein said apparatus outputs at least one of said analog component data signals as the improved data transmission signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
a peak detection mechanism coupled to at least one of said component data signals for detecting the peak amplitude of one of said component data signals, an automatic gain control mechanism coupled to said peak detector mechanism for dynamically adjusting gain control of said slicing mechanism, a frequency and phase acquisition mechanism coupled to said data clock reference signal from said phase lock loop mechanism and said external clock reference signal, said frequency and phase acquisition mechanism configured to acquire frequency and phase information, an equalizer tuning mechanism coupled to said gain and equalizing mechanism and said frequency and phase acquisition mechanism, said equalizer tuning mechanism configured to receive said frequency and phase acquisition information from said frequency and phase acquisition mechanism and supply said frequency and phase acquisition mechanism to said gain and equalizing mechanism to provide frequency and phase information feedback control. -
3. The apparatus of claim 2, wherein said decoding mechanism further includes,
a retimer mechanism coupled to said data clock reference signal from said phase lock loop mechanism and said digital component data signals, said retimer mechanism configured to synchronize said digital component data signals to said data clock reference signal. -
4. The apparatus of claim 3, further including,
a second coupler configured to couple said digital component data signals to said encoding mechanism. -
5. The apparatus of claim 4, wherein said encoding mechanism includes,
a multiplexer mechanism coupled to said digital component data signals and said data clock reference signal, said multiplexer mechanism configured to multiplex a plurality of digital signals, including said digital component signals, into said analog component signals. -
6. The apparatus of claim 5, wherein said encoding mechanism further includes,
a pulse shaping mechanism coupled to said digital component data signals, said pulse shaping mechanism configured to improve the shape of data pulses of said analog component signals, and an amplifier coupled to each of said analog component signals, said amplifier configured to amplify each of said analog component signals. -
7. The apparatus of claim 6, further including,
a third coupler configured to couple said amplified analog component signals to a data transmission facility comprising a link, said third coupler including a transformer configured to selectively couple at least one of said amplified analog component data signals to said data transmission facility as the improved data transmission signal.
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8. A communications system employing first and second communications processors disposed respectively at opposite ends of a communications link configured to receive a data transmission signal operating at a predetermined transmission rate and generating an improved data transmission signal to be transmitted across said communications link, said system comprising,
a first transceiver disposed at a hub end of said communications link that receives said data transmission signal, said first transceiver including said first communications processor for generating said improved data transmission signal, a first driver mechanism that prepares said improved data transmission signal for transmission across said communications link, and a first pre-processing mechanism that receives said improved data transmission from said communications link and supplying it to said communications processor; - and
a second transceiver disposed at a peripheral end of said communications link that receives said data transmission signal, said second transceiver including said communications processor for generating said improved data transmission signal, a second driver mechanism that prepares said improved data transmission signal for transmission across said communications link, and a peripheral pre-processing mechanism that receives said improved data transmission from said communications link and supplies it to said communications processor, wherein said each of said communications processors includes, a decoding mechanism that receives said data transmission signal and an external clock reference signal having a predetermined clock rate matching said predetermined transmission rate of said data transmission signal, said decoding mechanism configured to compensate for amplitude and phase distortions of said data transmission signal, to split said corrected data signal into component data signals, to generate a data clock reference signal based on said data transmission signal and said external clock reference signal, and to convert said component data signals into digital component data signals synchronized to said data clock reference signal, and an encoding mechanism coupled to said decoding mechanism, said encoding mechanism configured to receive said digital component data signals and said data clock reference signal and to convert said digital component data signals into analog component data signals, wherein each of said communications processors selectively outputs at least one of said analog component data signals as the improved data transmission signal. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
a first coupler and impedance matching mechanism configured to couple said data transmission signal to said decoding mechanism, said first coupler and impedance matching mechanism including a transformer having primary and secondary windings isolated from a ground connection, a resistive element matching the impedance of a transmission facility conveying said data transmission signal, and a high frequency coupling mechanism for filtering said coupled data transmission signal. -
10. The communications system of claim 9, wherein said decoding mechanism includes,
an attenuating mechanism coupled to said first coupler and impedance matching mechanism, said attenuating mechanism configured to initially adjust the amplitude of said coupled data transmission signal to a predetermined level. -
11. The communications system of claim 10, wherein said decoding mechanism further includes,
a gain and equalizing mechanism coupled to said attenuating mechanism, said gain and equalizing mechanism configured to adjust the gain and compensate for amplitude and phase distortions of said coupled data transmission signal, and a signal splitting mechanism to split the corrected data transmission signal into component data signals. -
12. The communications system of claim 11, wherein said decoding mechanism further includes,
a slicing mechanism coupled to said gain and equalizing mechanism and said signal splitting mechanism, said slicing mechanism configured to convert said component data signals into digital component data signals. -
13. The communications system of claim 12, wherein said decoding mechanism further includes,
a combiner mechanism coupled to said slicing mechanism, said combiner mechanism configured to combine said digital component data signals into a composite digital data signal, and a phase lock loop mechanism configured to receive said composite digital data signal, lock into a frequency and phase of said composite digital data signal, and generate said data clock reference signal, said phase lock loop mechanism including a phase detector to detect the phase of said composite digital data signal, a loop filter to filter out high frequency noise components of said composite digital signal, and a voltage controlled oscillator for generating said frequency and phase information from said composite digital signal. -
14. The communications system of claim 13, wherein said decoding mechanism further includes,
a peak detection mechanism coupled to at least one of said component data signals for detecting the peak amplitude of one of said component data signals, an automatic gain control mechanism coupled to said peak detector mechanism for dynamically adjusting gain control of said slicing mechanism, a frequency and phase acquisition mechanism coupled to said data clock reference signal from said phase lock loop mechanism and said external clock reference signal, said frequency and phase acquisition mechanism configured to acquire frequency and phase information, an equalizer tuning mechanism coupled to said gain and equalizing mechanism and said frequency and phase acquisition mechanism, said equalizer tuning mechanism configured to receive said frequency and phase acquisition information from said frequency and phase acquisition mechanism and supply said frequency and phase acquisition mechanism to said gain and equalizing mechanism to provide frequency and phase information feedback control. -
15. The communications system of claim 14, wherein said decoding mechanism further includes,
a retimer mechanism coupled to said data clock reference signal from said phase lock loop mechanism and said digital component data signals, said retimer mechanism configured to synchronize said digital component data signals to said data clock reference signal. -
16. The communications system of claim 15, wherein said communications processor further includes,
a second coupler configured to couple said digital component data signals to said encoding mechanism. -
17. The communications system of claim 16, wherein said encoding mechanism includes,
a multiplexer mechanism coupled to said digital component data signals and said data clock reference signal, said multiplexer mechanism configured to multiplex a plurality of digital signals, including said digital component signals, into said analog component signals. -
18. The communications system of claim 17, wherein said encoding mechanism further includes,
a pulse shaping mechanism coupled to said digital component data signals, said pulse shaping mechanism configured to improve the shape of data pulses of said analog component signals, and an amplifier coupled to each of said analog component signals, said amplifier configured to amplify each of said analog component signals. -
19. The communications system of claim 18, wherein said communications processor further includes,
a third coupler configured to couple said amplified analog component signals to a data transmission facility comprising a link, said third coupler including a transformer configured to selectively couple at least one of said amplified analog component data signals to said data transmission facility as the improved data transmission signal.
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20. An apparatus for transmitting a data transmission signal over a link, said apparatus comprising:
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a link having a transmit end and a receive end;
a first communications processor coupled to said transmit end for processing said data transmission signal before being transmitted over said link; and
a second communications processor coupled to said receive end for processing said data transmission signal before being received from said link;
said first communications processor comprising;
a first decoding mechanism configured to sample said data transmission signal to be transmitted at a clock rate and timing corresponding to points in time which said data transmission signal changes levels relative to the information being conveyed by said data transmission signal, the data transmission signal samples together forming a digital signal; and
a first encoding mechanism configured to receive said digital signal and to convert said digital signal into an analog data signal;
said second communications processor comprising;
a second decoding mechanism configured to sample said data transmission signal to be received at a clock rate and timing corresponding to points in time between which said data transmission signal relative to the information being conveyed by said data transmission signal, the data transmission signal samples together forming a digital signal; and a second encoding mechanism configured to receive said digital signal and to convert said digital signal into an analog data signal.
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Specification
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Current AssigneeBitRage, Inc.
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Original AssigneeBitRage, Inc.
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InventorsChea, Woody A.
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Primary Examiner(s)Tran, Khai
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Assistant Examiner(s)GHULAMALI, QUTBUDDIN
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Application NumberUS09/583,912Time in Patent Office1,637 DaysField of Search375/219, 375/220, 375/225, 375/229, 375/257, 375/355, 375/371, 375/344, 375/376, 375/316US Class Current375/219CPC Class CodesH04L 5/16 Half-duplex systems; Simple...
