Fault tolerant apparatus and method for determining a revolution rate of a gear

• US 6,823,275 B2
• Filed: 02/03/2004
• Issued: 11/23/2004
• Est. Priority Date: 05/02/2002
• Status: Expired due to Term

• Current Assignee: Schneider Electric Systems USA, Inc. (Schneider Electric SE)
• Original Assignee: Invensys Systems Incorporated (Invensys PLC)
• Inventors: Brown, David R., Rasmussen, David C., Meyer, Matthew C., Norris, Jeffrey A., Mishra, Ajay P.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Desta, Elias
• Application Number:
  US10/769,877
• Publication Number:
  US 20040158422A1
• Time in Patent Office: 294 Days
• Field of Search: 702/33, 702/56, 702/66, 702/75, 702/78-80, 702/113, 702/115, 702/124, 73/12.7, 732/04, 324/392, 324/676, 377/20, 377/29
• US Class Current: 702/79
• CPC Class Codes: G01P 3/489 Digital circuits therefor

Abstract

An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Claims

1. An apparatus comprising:

a pulse-input measurement system having at least three redundant subsystems, each subsystem having;

an input filter network configured to receive an input signal to produce a filtered signal;

a comparator coupled to the input filter network, the comparator configured to receive the filtered signal and to produce a comparator signal; and

an input-output controller coupled to the comparator, the input-out controller configured to receive the comparator signal and to produce a pulse-to-pulse delay value.

2. The apparatus of claim 1, wherein the at least three redundant subsystems each include:

an isolated bus transceiver coupled to the pulse-input module for that redundant subsystem, the isolated bus transceiver configured to receive the pulse-rate value and send an output signal for that redundant subsystem.

3. The apparatus of claim 1, further comprising:

at least three input/output bases each being uniquely coupled to the input-output controller of the at least three redundant subsystems of the pulse-input measurement system, each input/output bus being configured to receive the pulse-to-pulse delay value from the respective redundant subsystem of the pulse-input measurement system; and

at least three processors each being uniquely coupled to the at least three input/output buses, the at least three processors configured to receive the pulse-to-pulse delay value from the respective input/output bus, the at least three processors configured to send an optimal pulse-rate value based on the pulse-to-pulse delay value associated with each redundant subsystem.

4. The apparatus of claim 3, wherein the at least three processors are configured to calculate the optimal pulse-rate value by selecting a median of the pulse-rate value from each subsystem of the pulse-input measurement system when each pulse-rate value from each subsystem of the pulse-input measurement system has a non-zero value.

5. The apparatus of claim 3, wherein the at least three processors are configured to calculate the optimal pulse-rate value by averaging the pulse-rate value from each subsystem of the pulse-input measurement system when the pulse-rate value for one subsystem of the pulse-input measurement system has a zero value.

6. The apparatus of claim 3, wherein the at least three processors are configured to select the pulse-rate value from one redundant subsystem as the optimal pulse-rate value when the pulse-rate value for one redundant subsystem has a zero value, the selected pulse-rate value being a highest value.

7. The apparatus of claim 3, wherein when the pulse-rate value for one redundant subsystem has a zero value, the at least three processors are configured to calculate the optimal pulse-rate value by averaging the pulse-rate from the remaining redundant subsystems from the at least three redundant subsystems.

8. The apparatus of claim 3, wherein the at least three processors are configured to select the pulse-rate value from one redundant subsystem as the optimal pulse-rate value, when the pulse-rate value for that one redundant subsystems has a non-zero value and the pulse-rate values for the remaining redundant subsystems have a zero value.

9. The apparatus of claim 1, where the comparator of each subsystem includes complimentary hysteresis portions.