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Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

  • US 6,823,429 B1
  • Filed: 09/10/1999
  • Issued: 11/23/2004
  • Est. Priority Date: 07/10/1997
  • Status: Expired due to Fees
First Claim
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1. A cache coherency system for a shared memory parallel processing system including a plurality of processing nodes, comprising:

  • a single multi-stage communication network for interconnecting said processing nodes, said network including a dual priority switch at each node for selectively operating in normal low priority mode and camp-on high priority mode;

    each said processing node including a unique section of shared memory which is not a cache;

    each said processing node including one or more caches for storing a plurality of cache lines;

    a cache coherency directory which is distributed to each of said nodes for tracking which of one or more of said nodes have copies of each cache line; and

    an adapter for storing changed data immediately to said unique section of shared memory regardless of which of said nodes is changing the data and which of said nodes includes the section of shared memory to be changed, such that said shared memory always contains the most recent data according to a two hop process including in hop

         1) a requesting node requests most recent data of a home node, and in hop

         2) said home node immediately returns said most recent data from its shared memory to said requesting node.

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