Exception handling using an exception pipeline in a pipelined processor

• US 6,823,448 B2
• Filed: 12/15/2000
• Issued: 11/23/2004
• Est. Priority Date: 12/15/2000
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc., Intel Corporation
• Inventors: Roth, Charles P., Overkamp, Gregory A., Singh, Ravi P.
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): Gerstl, Shane
• Application Number:
  US09/738,081
• Publication Number:
  US 20020078334A1
• Time in Patent Office: 1,439 Days
• Field of Search: 712/244
• US Class Current: 712/244
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags

Abstract

A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.

Claims

1. A method comprising:

processing an instruction in an execution pipeline of a programmable processor; and

propagating an exception of the instruction through an exception pipeline of the processor;

wherein said propagating the exception through the exception pipeline comprises selecting one of a plurality of exceptions at an intermediate stage of the exception pipeline based on priority information associated with the exceptions, the plurality of exceptions including a first exception obtained from a previous stage and a second exception obtained at the intermediate stage, and propagating a selected exception to a subsequent stage of the exception pipeline.

2. The method of claim 1, wherein processing the instruction in the execution pipeline comprises propagating the instruction through N stages of the execution pipeline, and wherein said propagating the exception of the instruction through the exception pipeline comprises propagating the exception of the instruction through N stages of the exception pipeline.

3. The method of claim 1, further comprising receiving the propagated exception from the execution pipeline and storing the propagated exception within the exception pipeline.

4. The method of claim 3, wherein receiving the propagated exception comprises receiving an exception code from one of a plurality of stages of the execution pipeline, and further wherein storing the propagated exception includes storing the exception code within a corresponding stage of the exception pipeline.

5. The method of claim 1, wherein said propagating the exception through the exception pipeline further comprises propagating an exception request bit in the exception pipeline, wherein the exception request bit represents an error condition for an instruction within a corresponding stage of the execution pipeline.

6. The method of claim 1, further comprising stalling the exception pipeline when the execution pipeline is stalled.

7. The method of claim 1, further comprising clearing the propagated exception within the exception pipeline when a corresponding instruction within execution pipeline will not complete execution.

8. The method of claim 1, further comprising servicing the propagated exception when the propagated exception has propagated through a last stage of the exception pipeline.

9. The method of claim 1, further comprising qualifying the propagated exception at stages of the exception pipeline to ensure the corresponding instruction has not been terminated.

10. The method of claim 1, further comprising qualifying the propagated exception at stages of the exception pipeline, except an instruction fetch stage, to ensure the corresponding instruction is valid.

11. An apparatus comprising:

an execution pipeline having a plurality of stages to execute one or more instructions concurrently; and

an exception pipeline having a plurality of stages to propagate exceptions resulting from the execution of the instructions;

wherein the stages of the exception pipeline include at least one intermediate stage comprising an exception selection unit operable to select a highest priority exception from among a first exception obtained from a previous stage and a second exception obtained at the intermediate stage to be passed to a subsequent stage of the exception pipeline.

12. The apparatus of claim 11, wherein the execution pipeline and the exception pipeline each have N stages.

13. The apparatus of claim 11, wherein the stages of the exception pipeline include pipeline registers to store exception codes.

14. The apparatus of claim 11, wherein the stages of the exception pipeline and the execution pipeline are controlled by one or more stall signals.

15. The apparatus of claim 11, wherein the exception pipeline includes a plurality of storage circuits to propagate an exception request bit.

16. The apparatus of claim 15, wherein each stage of the exception pipline receives a kill signal to reset the exception request bit.

17. The apparatus of claim 15, further comprising an exception handler receiving the exception request bit from a last stage of the exception pipeline.

18. The apparatus of claim 15, wherein the stages of the exception pipeline include logic to qualify the exception request bit to ensure the instruction is a valid instruction and has not been terminated.

19. The apparatus of claim 11, wherein each of the stages of the exception pipeline includes selection logic to select one of a plurality of exceptions based on priority information associated with the exceptions.

20. A system comprising:

a Flash memory device; and

a processor coupled to the Flash memory device, wherein the processor includes an execution pipeline having a plurality of stages to execute one or more instructions concurrently, and an exception pipeline having a plurality of stages to propagate exceptions resulting from the execution of the instructions,

wherein the stages of the exception pipeline include at least one intermediate stage comprising an exception selection unit operable to select a highest priority exception from among a first exception obtained from a previous stage and a second exception obtained at the intermediate stage to be passed to a subsequent stage of the exception pipeline.

21. The system of claim 20, wherein the execution pipeline and the exception pipeline each have N stages.

22. The system of claim 20, wherein the stages of the exception pipeline include pipeline registers to store exception codes.

23. The system of claim 20, wherein the stages of the exception pipeline and the execution pipeline are synchronously controlled by one or more stall signals.

24. The system of claim 20, wherein the exception pipeline includes a plurality of storage circuits to propagate an exception request bit.

25. The system of claim 24, wherein the processor further comprises an exception handler receiving the exception request bit from a last stage of the exception pipeline.