Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem
First Claim
1. A processor, comprising:
- execution resources;
data storage; and
an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources;
wherein of said execution resources, said data storage, and said instruction sequencing unit, at least said execution resources are implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams, and wherein said instruction sequencing unit includes a hashing circuit that assigns said plurality of data streams to said plurality of hardware partitions based upon an address hash of addresses associated with instructions within said plurality of data streams, said hash being selected by a hash selection circuit within said processor, and wherein if an error is detected in a particular hardware partition among said plurality of hardware partitions that is assigned a particular data stream among said plurality of data streams to process, said hashing selection circuit reassigns said particular data stream to at least one other of said plurality of hardware partitions by changing the address hash implemented by the hashing circuit.
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Accused Products
Abstract
A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
57 Citations
15 Claims
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1. A processor, comprising:
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execution resources;
data storage; and
an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources;
wherein of said execution resources, said data storage, and said instruction sequencing unit, at least said execution resources are implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams, and wherein said instruction sequencing unit includes a hashing circuit that assigns said plurality of data streams to said plurality of hardware partitions based upon an address hash of addresses associated with instructions within said plurality of data streams, said hash being selected by a hash selection circuit within said processor, and wherein if an error is detected in a particular hardware partition among said plurality of hardware partitions that is assigned a particular data stream among said plurality of data streams to process, said hashing selection circuit reassigns said particular data stream to at least one other of said plurality of hardware partitions by changing the address hash implemented by the hashing circuit. - View Dependent Claims (2, 3, 4, 5)
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6. A data processing system, comprising:
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at least one interconnect;
at least one memory coupled to said interconnect; and
at least one processor coupled to said interconnect, wherein said processing includes;
execution resources;
data storage; and
an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources;
wherein of said execution resources, said data storage, and said instruction sequencing unit, at least said execution resources are implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams, and wherein said instruction sequencing unit includes a hashing circuit that assigns said plurality of data streams to said plurality of hardware partitions based upon an address hash of addresses associated with instructions within said plurality of data streams, said hash being selected by a hash selection circuit within said processor, and wherein if an error is detected in a particular hardware partition among said plurality of hardware partitions that is assigned a particular data stream among said plurality of data streams to process, said hashing selection circuit reassigns said particular data stream to at least one other of said plurality of hardware partitions by changing the address hash implemented by the hashing circuit. - View Dependent Claims (7, 8, 9, 10)
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11. A method of operating a processor, including execution resources, data storage, and an instruction sequencing unit, coupled to said execution resources and said data storage, that supplies instructions within said data storage to said execution resources, wherein of said execution resources, said data storage, and said instruction sequencing unit, at least said execution resources are implemented with a plurality of hardware partitions of like function, said method comprising:
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assigning a plurality of data streams to said plurality of hardware partitions based upon an address hash of addresses associated with instructions within said plurality of data streams;
processing each of the plurality of data streams within a respective one of the plurality of hardware partitions of like function; and
in response to detection of an error in a particular hardware partition among said plurality of hardware partitions that is processing a particular data stream among said plurality of data streams, reassigning said particular data stream to at least one other of said plurality of hardware partitions by changing said address hash. - View Dependent Claims (12, 13, 14, 15)
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Specification