Method and user interface for debugging an electronic system

• US 6,823,497 B2
• Filed: 07/31/2002
• Issued: 11/23/2004
• Est. Priority Date: 11/30/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synplicity, Inc. (Synopsys Incorporated)
• Inventors: Beardslee, John Mark, Schubert, Nils Endric, Koch, Gernot Heinrich, Poeppe, Olaf
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US10/210,509
• Publication Number:
  US 20030131325A1
• Time in Patent Office: 846 Days
• Field of Search: 716/2-6, 716/15, 716/18, 714/728, 714/724, 714/43, 713/2, 710/15, 703/26, 703/17, 703/16
• US Class Current: 716/106
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Claims

1. A method for facilitating debugging of a fabricated integrated circuit, said method comprising:

displaying, on a display device associated with a user, portions of a high level hardware description language (HDL) description of electronic circuitry to be included within the fabricated integrated circuit;

determining aspects of the electronic circuitry to be examined or modified during debugging of the fabricated integrated circuit, the aspects of the electronic circuitry being determined through selections made with respect to the high level HDL description of the electronic circuitry;

displaying, on the display device, a visual indication of the selections that have been made with respect to the high level HDL description of the electronic circuitry;

creating a design for design instrumentation circuitry based on the aspects of the electronic circuitry determined to be examined or modified; and

incorporating the design for the design instrumentation circuitry into the high level HDL description or a circuit representation derived from the high level HDL description of the electronic circuitry so as to facilitate debugging of the fabricated integrated circuit.

2. A method as recited in claim 1, wherein the selections made with respect to the high level HDL description are made automatically without user interaction.

3. A method as recited in claim 1, wherein the selections are automatically made by an instrumentor.

4. A method as recited in claim 1, wherein the selections made with respect to the high level HDL description are made through user interaction with a command line interface.

5. A method as recited in claim 1, wherein the selections made with respect to the high level HDL description are made either interactively or in batch mode at various levels of granularity.

6. A method as recited in claim 1, wherein said displaying of the visual indication of the selections that have been made displays tags with the displayed portions of the high level HDL description of the electronic circuitry.

7. A method as recited in claim 1, wherein said determining aspects permits alteration of the design instrumentation circuitry to tradeoff debugging coverage versus area cost.

8. A method as recited in claim 7, wherein said method further comprises:

displaying the area cost on the display device during or after said determining aspects.

9. A method as recited in claim 7, wherein the area cost is dependent on a target technology for the electronic circuitry.

10. A method as recited in claim 7, wherein the area cost is with respect to one of FPGA slices, PLD logic elements, or ASIC gate equivalents.

11. A method, comprising:

displaying a graphical user interface, the graphical user interface comprising;

(i) a hardware description language (HDL) code pane that displays at least a portion of HDL code that describes an electronic system design;

(ii) a design navigation pane that displays a navigable, hierarchical description of the electronic system design;

determining aspects of the electronic system to be examined or modified during debugging of the electronic system after fabrication of the electronic system, the aspects of the electronic system being determined through selections made with respect to the HDL code;

displaying, on a display device, a visual indication of the selections that have been made with respect to the HDL code;

creating a design for design instrumentation circuitry based on the aspects of the electronic system determined to be examined or modified;

incorporating the design of the design instrumentation circuitry into the HDL code or a circuit description derived from the HDL code; and

,

displaying debug information with a section of the HDL code, said debugging information a consequence of operating the electronic system in its target environment at its target speed.

12. The method as recited in claim 11, wherein the navigable, hierarchical description is displayed in said design navigation pane in a tree-like structure.

13. The method as recited in claim 11, wherein visual indicators are displayed in said HDL code pane interrelated with the HDL code.

14. The method as recited in claim 13, wherein the debugging information indicates the status of at least one of a break-point and a watch-point.

15. The method as recited in claim 13, wherein the debugging information indicates the status of at least one of design visibility and design patching.

16. The method as recited in claim 13, wherein the visual indicators indicate selections with respect to the HDL code being displayed in said HDL code pane.

17. The method as recited in claim 16, wherein said graphical user interface further comprises:

a status pane that displays status information pertaining to at least the selections.

18. The method as recited in claim 17, wherein said graphical user interface further comprises:

a command line interface pane capable of receiving a command input thereto.

19. The method as recited in claim 17, wherein said status pane and said command line interface share a common pane.

20. The method as recited in claim 11, wherein said graphical user interface further comprises:

a status and command line pane that displays status information pertaining to at least the selections and that of receiving a command input.

21. A computer readable medium that includes at least computer program code for facilitating debugging of a fabricated integrated circuit, said computer readable medium comprising:

computer program code for displaying portions of a high level hardware description language (HDL) description of electronic circuitry to be included within the fabricated integrated circuit;

computer program code for determining aspects of the electronic circuitry to be examined or modified_during debugging of the fabricated integrated circuit, the aspects of the electronic circuitry being determined through selections made with respect to the high level HDL description of the electronic circuitry;

computer program code for displaying a visual indication of the selections that have been made with respect to the high level HDL description of the electronic circuitry;

computer program code for creating a design for design instrumentation circuitry based on the aspects of the electronic circuitry determined to be examined or modified; and

computer program code for incorporating the design for the design instrumentation circuitry into the high level HDL description or a circuit representation derived from the high level HDL description of the electronic circuitry to facilitate debugging of the fabricated integrated circuit.

22. A computer readable medium as recited in claim 21, wherein the selections made with respect to the high level HDL description are made automatically without user interaction.

23. A computer readable medium as recited in claim 21, wherein the selections made with respect to the high level HDL description are made through user interaction with a command line interface.

24. A computer readable medium as recited in claim 21, wherein the selections made with respect to the high level HDL description are made either interactively or in batch mode at various levels of granularity.

25. A computer readable medium as recited in claim 21, wherein said computer program code for displaying of the visual indication of the selections that have been made displays tags with the displayed portions of the high level HDL description of the electronic circuitry.

26. A computer readable medium as recited in claim 21, wherein said computer program code for determining the aspects of the electronic circuitry permits alteration of the design instrumentation circuitry to tradeoff debugging coverage versus area cost.

27. A computer readable medium as recited in claim 26, wherein said computer readable medium further comprises:

computer program code for displaying the area cost.

28. A computer readable medium as recited in claim 26, wherein the cost area is dependent on a target technology for the electronic circuitry.

29. A computer readable medium as recited in claim 21, wherein said computer readable medium further comprises:

computer program code for displaying portions of the high level HDL description with HDL-related debug information related thereto.

30. A computer readable medium as recited in claim 29, wherein said computer program code for displaying portions of the high level HDL description with HDL-related debug information related thereto operates to display the HDL-related debug information as visual indicators on the HDL-related debug information being displayed.

31. A computer readable medium as recited in claim 30, wherein the visual indicators are tags.

32. A computer readable medium that includes at least computer program code for facilitating debugging of a fabricated integrated circuit, said computer readable medium comprising:

computer program code for displaying a graphical user interface, the graphical user interface comprising;

(i) a hardware description language (HDL) code pane that displays at least a portion of HDL code that describes an electronic system design;

(ii) a design navigation pane that displays a navigable, hierarchical description of the electronic system design;

computer program code for determining aspects of the electronic system to be examined or modified during debugging of the electronic system after fabrication of the electronic system, the aspects of the electronic system being determined through selections made with respect to the HDL code that describes the electronic system;

computer program code for displaying, on a display device, a visual indication of the selections that have been made with respect to the HDL code that describes the electronic system;

computer program code for creating a design for design instrumentation circuitry based on the aspects of the electronic system determined to be examined or modified;

computer program code for incorporating the design for the design instrumentation circuitry into the HDL code or a circuity description derived from the HDL code that describes the electronic system; and

,

computer program code for displaying debug information with a section of the HDL code that describes the electronic system, said debugging information a consequence of operating the electronic system in its target environment at its target speed.

33. A computer readable medium as recited in claim 32, wherein the navigable, hierarchical description is displayed in said design navigation pane in a tree-like structure.

34. A computer readable medium as recited in claim 32, wherein visual indicators are displayed in said HDL code pane interrelated with the HDL code.

35. A computer readable medium as recited in claim 34, wherein the debugging information indicates the status of at least one of a break-point and a watch-point.

36. A computer readable medium as recited in claim 34, wherein the debugging information indicates the status of at least one of design visibility and design patching.

37. A computer readable medium as recited in claim 34, wherein the visual indicators indicate selections with respect to the HDL code being displayed in said HDL code pane.

38. A computer readable medium as recited in claim 37, wherein said graphical user interface further comprises:

a status pane that displays status information pertaining to at least the selections.

39. A computer readable medium as recited in claim 38, wherein said graphical user interface further comprises:

a command line interface pane capable of receiving a command input thereto.

40. A computer readable medium as recited in claim 38, wherein said status pane and said command line interface share a common pane.

41. A computer readable medium as recited in claim 32, wherein said graphical user interface further comprises:

a status and command line pane that displays status information pertaining to at least the selections and that of receiving a command input.