Method of generating the padring layout design using automation

• US 6,823,501 B1
• Filed: 10/03/2002
• Issued: 11/23/2004
• Est. Priority Date: 11/28/2001
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: ReShape, Inc. (Synopsys Incorporated)
• Inventors: Dahl, Peter
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US10/264,680
• Time in Patent Office: 782 Days
• Field of Search: 716/1, 716/8-14
• US Class Current: 716/122
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

Methods for generating a padring layout design are described. These methods utilize automation while still allowing customization. Automation is emphasized as much as possible so that more time can be used to solve the various problems that make each padring layout design unique. A framework in which regular patterns can be described, replicated, and tailored is provided. The padring is broken down into zones in which slots having bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas are laid out in a regular pattern through an instantiation process. Edge logic, which is comprised of standard cells, is pulled from the core of the chip because these cells couple directly to I/O cells and are critical for timing. The framework allows the bumps/bond pads, I/O cells, and edge logic cells to be laid out in respective bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas according to algorithms associated with the patterns and using a variety of maps which associate the logical netlist with the physical layout design.

Claims

1. A method of generating a padring layout design for a chip design, comprising:

a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;

b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas;

c) using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone; and

d) placing one or more objects in said areas of said slots.

2. The method as recited in claim 1 wherein one of said areas comprises a bump area for placing a bump.

3. The method as recited in claim 1 wherein one of said areas comprises a bond pad area for placing a bond pad.

4. The method as recited in claim 1 wherein one of said areas comprises an I/O area for placing one or more I/O cells.

5. The method as recited in claim 1 wherein one of said areas comprises an edge logic area for placing one or more standard cells which are associated with an I/O cell.

6. The method as recited in claim 5 wherein said edge logic area overlaps a core region of said chip design.

7. The method as recited in claim 1 wherein said step b) comprises:

forming said pattern using an editor.

8. The method as recited in claim 1 wherein said step b) comprises:

forming said pattern using a graphical user interface (GUI).

9. The method as recited in claim 1 wherein said step b) comprises:

selecting said pattern from a library comprising a plurality of previously generated patterns.

10. The method as recited in claim 1 wherein said step b) comprises:

defining said pattern with a software program.

11. The method as recited in claim 1 wherein said padring layout design is a linear padring layout design.

12. The method as recited in claim 1 wherein said padring layout design is a BGA padring layout design.

13. A method for generating a padring layout design for a chip design, comprising:

a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;

b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas;

c) for each respective zone, selecting a corresponding pattern;

d) placing said corresponding pattern within said respective zone;

e) creating said one or more slots according to said corresponding pattern so that each area of each slot is associated with a particular location in said respective zone;

f) moving said corresponding pattern to another position within said respective zone;

g) repeating said steps e) and f) as specified by a placement algorithm; and

h) placing one or more objects in said areas of said slots.

14. The method as recited in claim 13 wherein one of said areas comprises a bump area for placing a bump.

15. The method as recited in claim 13 wherein one of said areas comprises a bond pad area for placing a bond pad.

16. The method as recited in claim 13 wherein one of said areas comprises an I/O area for placing one or more I/O cells.

17. The method as recited in claim 13 wherein one of said areas comprises an edge logic area for placing one or more standard cells which are associated with an I/O cell.

18. The method as recited in claim 17 wherein said edge logic area overlaps a core region of said chip design.

19. The method as recited in claim 13 wherein said step b) comprises:

forming said pattern using an editor.

20. The method as recited in claim 13 wherein said step b) comprises:

forming said pattern using a graphical user interface (GUI).

21. The method as recited in claim 13 wherein said step b) comprises:

selecting said pattern from a library comprising a plurality of previously generated patterns.

22. The method as recited in claim 13 wherein said step b) comprises:

defining said pattern with a software program.

23. The method as recited in claim 13 wherein said padring layout design is a linear padring layout design.

24. The method as recited in claim 13 wherein said padring layout design is a BGA padring layout design.

25. A computer system comprising:

a processor; and

a memory device coupled to said processor, wherein said memory device comprises computer-executable instructions stored therein for performing a method of generating a padring layout design for a chip design, comprising;

a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;

b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas;

c) using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone; and

d) placing one or more objects in said areas of said slots.

26. The computer system as recited in claim 25 wherein one of said areas comprises a bump area for placing a bump.

27. The computer system as recited in claim 25 wherein one of said areas comprises a bond pad area for placing a bond pad.

28. The computer system as recited in claim 25 wherein one of said areas comprises an I/O area for placing one or more I/O cells.

29. The computer system as recited in claim 25 wherein one of said areas comprises an edge logic area for placing one or more standard cells which are associated with an I/O cell.

30. The computer system as recited in claim 29 wherein said edge logic area overlaps a core region of said chip design.

31. The computer system as recited in claim 25 wherein said step b) comprises:

forming said pattern using an editor.

32. The computer system as recited in claim 25 wherein said step b) comprises:

forming said pattern using a graphical user interface (GUI).

33. The computer system as recited in claim 25 wherein said step b) comprises:

selecting said pattern from a library comprising a plurality of previously generated patterns.

34. The computer system as recited in claim 25 wherein said step b) comprises:

defining said pattern with a software program.

35. The computer system as recited in claim 25 wherein said padring layout design is a linear padring layout design.

36. The computer system as recited in claim 25 wherein said padring layout design is a BGA padring layout design.

37. A computer system comprising:

a processor; and

a memory device coupled to said processor, wherein said memory device comprises computer-executable instructions stored therein for performing a method for generating a padring layout design for a chip design, comprising;

a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;

b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas;

c) for each respective zone, selecting a corresponding pattern;

d) placing said corresponding pattern within said respective zone;

e) creating said one or more slots according to said corresponding pattern so that each area of each slot is associated with a particular location in said respective zone;

f) moving said corresponding pattern to another position within said respective zone;

g) repeating said steps e) and f as specified by a placement algorithm; and

h) placing one or more objects in said areas of said slots.

38. The computer system as recited in claim 37 wherein one of said areas comprises a bump area for placing a bump.

39. The computer system as recited in claim 37 wherein one of said areas comprises a bond pad area for placing a bond pad.

40. The computer system as recited in claim 37 wherein one of said areas comprises an I/O area for placing one or more I/O cells.

41. The computer system as recited in claim 37 wherein one of said areas comprises an edge logic area for placing one or more standard cells which are associated with an I/O cell.

42. The computer system as recited in claim 41 wherein said edge logic area overlaps a core region of said chip design.

43. The computer system as recited in claim 37 wherein said step b) comprises:

forming said pattern using an editor.

44. The computer system as recited in claim 37 wherein said step b) comprises:

forming said pattern using a graphical user interface (GUI).

45. The computer system as recited in claim 37 wherein said step b) comprises:

selecting said pattern from a library comprising a plurality of previously generated patterns.

46. The computer system as recited in claim 37 wherein said step b) comprises:

defining said pattern with a software program.

47. The computer system as recited in claim 37 wherein said padring layout design is a linear padring layout design.

48. The computer system as recited in claim 37 wherein said padring layout design is a BGA padring layout design.