Test assembly including a test die for testing a semiconductor product die

• US 6,825,052 B2
• Filed: 12/11/2002
• Issued: 11/30/2004
• Est. Priority Date: 01/15/1997
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Eldridge, Benjamin N., Khandros, Igor Y., Pedersen, David V., Whitten, Ralph G.
• Primary Examiner(s): Thompson, Craig A.
• Assistant Examiner(s): BEREZNY, NEMA O
• Application Number:
  US10/317,486
• Publication Number:
  US 20040004216A1
• Time in Patent Office: 720 Days
• Field of Search: 438/15, 438/14, 438/18, 324/527, 324/528, 324/754, 324/755, 324/763, 324/765
• US Class Current: 438/15
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/3421 : Leaded components

Abstract

One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.

Claims

1. A method of testing circuitry of a semiconductor die said method comprising:

contacting with a first probe card a plurality of bond pads, wherein said circuitry of said semiconductor die is configured to input signals and output signals through said bond pads; and

contacting with a second probe card a plurality of special pads, each of said special pads being electrically connected directly to an internal portion of said circuitry,

wherein said special pads are electrically insulated from said bond pads.

2. The method of claim 1 further comprising:

running a first test of said circuitry of said die while said first probe card is contacting said bond pads; and

running a second test of said circuitry of said die while said second probe card is contacting said bond pads.

3. The method of claim 2 further comprising a first test die disposed on said first probe card, wherein said first test die performs a function that corresponds to said first test.

4. The method of claim 3, wherein said first test die is in communication with a tester, and said tester and said first test die perform functions that correspond to said first test.

5. The method of claim 3 further comprising a plurality of said first test dies.

6. The method of claim 5, wherein one of said plurality of first test dies is a shared test die that performs a test function common to others of said plurality of first test dies.

7. The method of claim 2, wherein:

said first test tests overall operation of said circuitry, and

said second test tests operation of only a portion of said circuitry.

8. The method of claim 2, wherein said first test comprises:

inputting first test data into ones of said bond pads, and

reading first response data output through others of said bond pads,

wherein said internal circuitry generates said first response data from said first test data.

10. The method of claim 1 further comprising a second test die disposed on said second probe card, wherein said second test die perform a function that corresponds to said second test.

11. The method of claim 10 further comprising a plurality of said second test dies.

12. The method of claim 11, wherein one of said plurality of second test dies is a shared test die that performs a test function common to others of said plurality of first test dies.

13. The method of claim 10, wherein said second test die is in communication with a tester, and said tester and said second test die perform functions that correspond to said second test.

14. The method of claim 1, wherein said bond pads extend to a first height from a surface of said die and said special bond pads extend to a second height from a surface of said die, wherein said first height is greater than said second height.

15. The method of claim 1, wherein:

said internal circuitry comprises internal test circuitry for testing said circuitry of said die, and

at least one of said special pads is electrically connected to said internal test circuitry.

16. The method of claim 15, wherein said at least one special pad provides at least one control signal to said internal test circuitry.

17. The method of claim 1, wherein:

each of said bond pads comprises first electrostatic discharge protection circuitry,

each of said special pads comprises second electrostatic discharge protection circuitry, and

said first electrostatic discharge protection circuitry provides protection against a larger electrostatic discharge than said second electrostatic discharge circuitry.

9. The method of 8, wherein said internal circuitry comprises a plurality of subcircuits, and said second test comprises:

inputting through ones of said special pads second test data to inputs of one of said subcircuits, and

reading through other ones of said special pads second response data generated by said one of said subcircuits.