Twin NAND device structure, array operations and fabrication method

• US 6,825,084 B2
• Filed: 10/30/2003
• Issued: 11/30/2004
• Est. Priority Date: 08/13/2001
• Status: Expired due to Term

• Current Assignee: Halo LSI, Inc.
• Original Assignee: Halo LSI, Inc.
• Inventors: Ogura, Seiki, Saito, Tomoya, Ogura, Tomoko, Satoh, Kimihiro
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US10/697,520
• Publication Number:
  US 20040092066A1
• Time in Patent Office: 397 Days
• Field of Search: 438/262, 438/264, 438/263, 438/258, 438/279, 438/257, 438/200, 438/197, 438/680, 365/185.17, 365/185.12, 365/185.24, 365/49, 365/54, 365/189.01, 365/190, 365/154, 365/185.06, 365/185.13, 365/185.25, 365/185.33
• US Class Current: 438/262
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

Claims

1. A method for block erase of storage sites of a twin MONOS NAND memory array, comprising:

a) applying a high positive voltage to a selected word line,

b) applying a low voltage to unselected word lines,

c) applying a ground potential to a drain of an upper column selector gate,

e) applying a ground potential to a source of a lower column selector,

f) selecting said upper and lower column selectors and erasing both storage sites of each cell in a block of cells.

2. The method for block erase of claim 1, wherein said low voltage is of sufficient magnitude to allow the ground potential to be connected to a source and a drain of each cell in said block of cells through unselected cell in each column containing said block.

3. The method for block erase of claim 1, wherein erasing storage sites is an operation whereby electrons are injected into said storage sites by FN tunneling.

4. A method of programming storage sites in a twin MONOS NAND array, comprising:

a) selecting a first storage site to be programmed of two storage sites contained within a selected memory cell of a column memory cells,

b) connecting a negative voltage to a word gate of said selected memory cell,

c) connecting a positive voltage to a first diffusion extending under said first storage site,

d) connecting a ground potential to a second diffusion extending under a second storage site of said two storage sites,

e) programming said first storage site.

5. The method of programming of claim 4, wherein programming said first storage site is an operation whereby electrons are ejected from said first storage site by FN tunneling or hole injection.

6. The method of programming of claim 4, wherein connecting said positive voltage to said first diffusion further comprises:

a) connecting said positive voltage from a column selector gate by selecting said selector gate,

b) connecting a word line voltage higher in value than said positive voltage to unselected word gates in said column between said column selector gate and said first diffusion.

7. The method of programming of claim 4, wherein connecting said ground potential to said second diffusion further comprises:

a) connecting said ground potential from a column selector gate by selecting said selector gate,

b) connecting a word line voltage higher in value than said ground potential to unselected word gates in said column between said column selector gate and said second diffusion.

8. A method of reading storage sites in a twin MONOS NAND array, comprising:

a) selecting a first storage site to be read from two storage sites contained within a selected memory cell of a column memory cells,

b) connecting a first positive voltage to a word gate of said selected memory cell,

c) connecting a ground potential to a first diffusion extending under said first storage site to be read,

c) connecting a second positive voltage to a second diffusion extending under a second storage site not being read,

e) reading a current when the word gate voltage becomes higher than cell thresh hold voltage depending upon the data stored in said first storage site.

9. The method of reading storage sites of claim 8, wherein said first positive voltage is a value near a programmed threshold voltage of said memory cell.

10. The method of reading storage sites of claim 8, wherein said second positive voltage is less than said first positive voltage.

11. The method of reading storage sites of claim 8, wherein connecting said ground potential to said first diffusion further comprises:

a) selecting a column selector gate connecting said ground potential to said column,

b) applying a positive voltage to word lines of unselected memory cells between said column selector and said first diffusion.

12. The method of reading storage sites of claim 8, wherein connecting said second positive voltage to said second diffusion further comprises:

a) selecting a column selector gate connecting said second positive voltage to said column,

b) applying a positive voltage to word lines of unselected memory cells between said column selector and said second diffusion.

13. The method of reading storage sites of claim 8 further comprising:

a) said second positive voltage connected to said second diffusion produces a low threshold voltage for said second storage site,

b) said first storage site has a high threshold voltage when charged with electrons representing said first storage site not being programmed thereby blocking a flow of current,

c) said first storage site has said low threshold voltage when not charged with electrons representing said first storage site being programmed thereby allowing said flow of current,

d) said flow of current indicates a stored data value in said first storage site.